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| BQ76PL536-Q1 www.ti.com slusab1 C may 2011 3 to 6 series cell lithium-ion battery monitor and secondary protection ic for ev and hev applications check for samples: BQ76PL536-Q1 1 features applications ? electric and hybrid electric vehicles 2 ? 3 to 6 series cell support, all chemistries ? e-bike and e-scooter ? hot-pluggable ? uninterruptible power systems (ups) ? high-speed spi for data communications ? large-format battery systems ? stackable vertical interface ? no isolation components required between description ics the bq76pl536 -q1 is a stackable three to six series ? qualified for automotive applications cell lithium-ion battery pack protector and analog front end (afe) that incorporates a precision ? temperature range C 40 c to 105 c analog-to-digital converter (adc); independent cell ? high-accuracy analog-to-digital converter voltage and temperature protection; cell balancing, (adc): and a precision 5-v regulator to power user circuitry. C 1 mv typical accuracy the bq76pl536 -q1 integrates a voltage translation C 14-bit resolution, 6- s conversion time and precision analog-to-digital converter system to C nine adc inputs: 6 cell voltages, 1 six-cell measure battery cell voltages with high accuracy and speed. brick voltage, 2 temperatures, 1 general-purpose input the bq76pl536 -q1 provides full protection C dedicated pins for synchronizing (secondary protection) for overvoltage, undervoltage, measurements and overtemperature conditions. when safety thresholds are exceeded, the bq76pl536 -q1 sets the ? configuration data stored in ecc-otp fault output. no external components are needed registers to configure or enable the protection features. ? built-in comparators (secondary protector) cell voltage and temperature protection functions are for: independent of the adc system. programmable C over- and undervoltage protection protection thresholds and detection delay times are C overtemperature protection stored in error check/correct (ecc) otp eprom, which increases the flexibility and reliability of the C programmable thresholds and delay times battery management system. C dedicated fault output signals the bq76pl536 -q1 is intended to be used with a ? cell balancing control outputs with safety host controller to maximize the functionality of the timeout battery management system. however, the protection C balance current set by external functions do not require a host controller. components the bq76pl536 q1 can be stacked vertically to ? supply voltage range from 6 v to 30 v monitor up to 192 cells without additional isolation continuous and 36 v peak components between ics. a high-speed serial ? low power: peripheral interface (spi) bus operates between each bq76pl536 -q1 to provide reliable communications C typical 12- a sleep, 45- a idle through a high-voltage battery cell stack. ? integrated precision 5-v, 3-ma ldo 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 powerpad is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
BQ76PL536-Q1 slusab1 C may 2011 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. description (continued) the host microcontroller controls cell balancing of individual cells by setting registers (via spi) which control the appropriate cbx outputs. these outputs can be turned off via the same control, or automatically by the internal programmable safety timer. the balancing bypass current is set via an external series resistor and fet. typical implementation figure 1. simplified system connection pin details pin functions pin type (1) description name no. agnd 15 ai internal analog v ref ( C ) alert_h 38 o host-to-device interface C alert condition detected in this or higher (north) device alert_n 57 i current-mode input indicating a system status change from the next-higher bq76pl536 -q1 alert_s 23 od current-mode output indicating a system status change to the next lower bq76pl536 -q1 aux 31 o switched 1-ma limited output from reg50 bat1 63 p power-supply voltage, connect to most-positive cell +, tie to bat2 on pcb (1) key: i = digital input, ai = analog input, o = digital output, od = open-drain output, t = 3-state output, p = power. 2 copyright ? 2011, texas instruments incorporated alert fault drdy spi drdy fault alert spi pack- pack+ host interface gpai gpio aux reg50 spi (north) ho s t i nt erf ace conv conv cbx (6) control (north) cell_1 cell_6 ??? cell_2-5 ??? alert fault drdy spi gpai gpio aux spi (north) ho s t i nt erf ace (n o t u sed ) conv cbx (6) control (north) bq76pl536q1 cell_1 cell_6 ??? cell_2-5 ??? to next device control (south) spi (south) south interface (not used on bottom device) bq76pl536q1 BQ76PL536-Q1 www.ti.com slusab1 C may 2011 pin type (1) description name no. bat2 64 p power-supply voltage, connect to most-positive cell +, tie to bat1 on pcb cb1 12 o cell-balance control output cb2 10 o cell-balance control output cb3 8 o cell-balance control output cb4 6 o cell-balance control output cb5 4 o cell-balance control output cb6 2 o cell-balance control output conv_h 36 i host-to-device interface C initiates a synchronous conversion. pin has 250-na internal sink to vss. conv_n 59 od current-mode output to the next-higher bq76pl536 -q1 to initiate a conversion conv_s 21 i input from the adjacent lower bq76pl536 -q1 to initiate a conversion cs_h 43 i host-to-device interface C active-low chip select from host. internal 100-k pullup resistor cs_n 52 od current-mode output used to select the next-higher bq76pl536 -q1 for spi communication cs_s 29 i current-mode input spi chip-select (slave-select) from the next-lower bq76pl536 -q1 drdy_h 37 o host-to-device interface C conversion complete, data-ready indication drdy_n 58 i current-mode input indicating conversion data is ready from next-higher bq76pl536 -q1 drdy_s 22 od current-mode output indicating conversion data is ready to the next lower bq76pl536 -q1 fault_h 39 o host-to-device interface C fault condition detected in this or higher (north) device fault_n 56 i current-mode input indicating a system status change from the next-higher bq76pl536 -q1 fault_s 24 od current-mode output gpai+ 48 ai general-purpose (differential) analog input, connect to vss if unused. gpai C 47 ai general-purpose (differential) analog input, connect to vss if unused. gpio 45 iod digital open-drain i/o. a 10-k to 2-m pullup is recommended. hsel 44 i host interface enable, 0 = enable, 1 = disable ldoa 17 p internal analog 5-v ldo bypass connection, requires 2.2- f ceramic capacitor for stability ldod1 18 p internal digital 5-v ldo bypass connection 1, requires 2.2- f ceramic capacitor for stability. this pin is tied internally to ldod2. this pin should be tied to ldod2 externally. ldod2 46 p internal digital 5-v ldo bypass connection 2, requires 2.2- f ceramic capacitor for stability. this pin is tied internally to ldod1. this pin should be tied to ldod1 externally. nc30 30 C no connection nc51 51 C no connect nc62 62 C no connect reg50 32 p 5-v user ldo output, requires 2.2- f ceramic capacitor for stability sclk_h 40 i host-to-device interface C spi clock from host sclk_n 55 od current-mode output spi clock to the next-higher bq76pl536 -q1 sclk_s 26 i current-mode input spi clock from the next-lower bq76pl536 -q1 sdi_h 42 i host-to-device interface C data from host to device (host mosi signal) sdi_n 53 od current-mode output for spi data to the next-higher bq76pl536 -q1 sdi_s 28 i current-mode input for spi data from the next-lower bq76pl536 -q1 sdo_h 41 o host-to-device interface C data from device to host (host miso signal), 3-state pin, 250-na internal pullup sdo_n 54 i current-mode input for spi data from the next-lower bq76pl536 -q1 sdo_s 27 od current-mode output for spi data to the next-lower bq76pl536 -q1 test 50 i factory test pin. connect to vss in user circuitry. this pin includes ~100-k internal pulldown ts1+ 20 ai differential temperature sensor input ts1 C 19 ai differential temperature sensor input ts2+ 61 ai differential temperature sensor input ts2 C 60 ai differential temperature sensor input vc0 13 ai sense-voltage input terminal for negative terminal of first cell (vss) vc1 11 ai sense voltage input terminal for positive terminal of the first cell copyright ? 2011, texas instruments incorporated 3 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com pin type (1) description name no. vc2 9 ai sense voltage input terminal for the positive terminal of the second cell vc3 7 ai sense voltage input terminal for the positive terminal of the third cell vc4 5 ai sense voltage input terminal for the positive terminal of the fourth cell vc5 3 ai sense voltage input terminal for the positive terminal of the fifth cell vc6 1 ai sense voltage input terminal for the positive terminal of the sixth cell vref 16 p internal analog voltage reference (+), requires 10- f, low-esr ceramic capacitor to agnd for stability vss 14, p v ss 33, 34, 35 vssd 25, 49 p v ss thermal C C thermal pad on bottom of powerpad ? package; this must be soldered to similar-size copper area on pad pcb and connected to vss, to meet stated specifications herein. provides heat-sinking to part. pinout diagram 4 copyright ? 2011, texas instruments incorporated cb2 vc1 vss conv_h agnd vss ts1+ sclk_s vssd fault_s drdy_s alert_s vss conv_s nc30 ts1C vref ldoa sdi_s cs_s cb1 vc0 vss sdo_s ldod1 aux vc3 reg50 drdy_h alert_h fault_h sclk_h sdo_h sdi_h cb4 vc4 hsel vc5 cb6 drdy_n conv_n sclk_nsdo_n gpaiC ldod2 bat1 nc62 nc51test cs_h cb3 vc2 vc6 bat2 ts2C ts2+ sdi_ncs_n gpai+ vssd cb5 alert_n fault_n gpio 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 3938 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p0071-04 pap package (top view) bq78pl536 tqfp-64 BQ76PL536-Q1 www.ti.com slusab1 C may 2011 ordering information t a package part no. C 40 c to 105 c 64 tqfp powerpad bq76pl536tpapq1 (1) package (1) the bq76pl536tpapq1 can be ordered in tape and reel as bq76pl536tpaptq1 (quantity 1000) or bq76pl536tpaprq1 (quantity 250). functional block diagram figure 2. bq76pl536 -q1 block diagram copyright ? 2011, texas instruments incorporated 5 5v ldo (user circuitry) vc2 reg50 gpaiC gpai+ gpio aux 14 bit adc vc1 vc3 vc4 vc5 vc6 cb2 cb1 cb3 cb4 cb5 cb6 ldo-a ldo-d ldoa ldod vc0 ref2 ov uv ov uv ov uv ov uv ov uv ov uv cell balancing +- ts1C ts1+ ts2C ts2+ ot1 ot2 vbat v ref 2.5v ultra-precision bandgap vref fault _s sclk_s sdi_s sdo_s cs_s alert_s conv_s drdy_s fault _n sclk_n sdi_n sdo_n cs_n alert_n conv_n drdy_n fault _h sclk_h sdi_h sdo_h cs_h alert_h conv_h drdy_h thermal shutdown bq76pl536 1.25v ref2 agnd host interface digital control logic registers eprom osc shifted north comms interface level shifted south comms interface level shift and mux analog communications power digital protector vss vssd vss BQ76PL536-Q1 slusab1 C may 2011 www.ti.com absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) value unit supply voltage range, v max bat1 , bat2 (2) C 0.3 to 36 v vc1 C vc6 C 0.3 to 36 vc0 C 0.3 to 2 vcn to vcn-1, n=1 to 6 0 to 36 ts1+, ts1 C , ts2+, ts2 C C 0.3 to 6 input voltage range, v in v gpai C 0.3 to 6 gpio C 0.3 to v reg50 + 0.3 drdy_n, sdo_n, fault_n, alert_n v bat C 1 to v bat + 2 conv_s, sdi_s, sclk_s, cs_s C 2 to 1 conv_n, sdi_n, sclk_n, cs_n C 0.3 to 36 drdy_s, sdo_s, fault_s, alert_s C 0.3 to 5 output voltage range, v o gpio C 0.3 to v reg50 + 0.3 v cb1 cb6 (cbref = 0x00) C 0.3 to 36 reg50, aux C 0.3 to 6 junction temperature 150 c storage temperature range, t stg C 65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages are with respect to vss of this device except vcn C vc(n+1), where n = 1 to 6 cell voltage. recommended operating conditions typical values stated where t a = 25 o c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 o c and bat = 7.2 v to 30 v (unless otherwise noted) min nom max unit v bat supply voltage bat 7.2 27 v vcn C vc(n C 1) (1) 1 4.5 gpai 0 2.5 gpio 0 v reg50 cbn (1) vc(n C 1) vcn v i , input voltage ts1+, ts1 C , ts2+, ts2 C 0 v reg50 /2 v range non-top ic in stack drdy_n, sdo_n, fault_n, alert_n bat + 1 top ic in stack drdy_n, sdo_n, fault_n, alert_n bat non-bottom ic in stack conv_s, sdi_s, sclk_s, cs_s C 1 bottom ic in stack conv_s, sdi_s, sclk_s, cs_s vss non-bottom ic in stack conv_n, sdi_n, sclk_n, cs_n 1 v o , bottom ic in stack conv_n, sdi_n, sclk_n, cs_n vss output v voltage non-top ic in stack drdy_s, sdo_s, fault_s, alert_s bat C 1 range top ic in stack drdy_s, sdo_s, fault_s, alert_s bat c reg50 external capacitor reg50 pin 2.2 f c vref external capacitor v ref pin 9.2 10 15 f c ldo external capacitor ldox pin 2.2 3.3 f t opr operating temperature (2) C 40 105 c (1) n = 1 to 6 (2) device specifications stated within this range. 6 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 electrical characteristics supply current typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min typ max unit no load at reg50, sclk_n, sdi_n, sdo_n, fault_n, conv_n, drdy_s, alert_n, tsx, aux, or cbx; icc sleep supply current 12 20 a cb_ctrl = 0; cbt_control = 0; conv_h = 0 (not converting), io_ctrl[sleep] = 1 no load at reg50, sclk_n, sdi_n, sdo_n, fault_n, conv_n, drdy_s, alert_n, tsx, aux, or cbx; icc protect supply current 45 60 a cb_ctrl = 0; cbt_control = 0; conv_h = 0 (not converting), io_ctrl[sleep] = 0 no load at reg50, sclk_n, sdi_n, sdo_n, fault_n, conv_n, drdy_s, alert_n, tsx, or aux; icc balance supply current 46 60 a no dc load at cbx; cb_ctrl 0; cbt_control 0; conv_h = 0 (not converting) , io_ctrl[sleep] = 0 no load at reg50, sclk_n, sdi_n, sdo_n, fault_n, icc convert supply current conv_n, drdy_s, alert_n, tsx or cbx; conv_s = 1 10.5 15 ma (conversion active) , io_ctrl[sleep] = 0 icc tsd supply current thermal shutdown activated; alert_status[tsd] = 1 1.6 ma reg50, integrated 5-v ldo typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min typ max unit v reg50 output voltage i reg50out 0.5 ma, c = 2.2 f to 22 f 4.9 5 5.1 v v reg50line line regulation 6 v bat 27 v, i reg50out = 2 ma 10 25 mv 0.2 ma i reg50out 2 ma 15 v reg50load load regulation mv 0.2 ma i reg50out 5 ma 25 i reg50max current limit 12 25 35 ma i auxmax maximum load aux pin 5 ma i = 1 ma, max. capacitance = v reg50 r aux aux output 50 capacitor: c vaux c vreg50 / 10 level shift interface typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min typ max unit i ntx1 north 1 transmitter current sclk_n, cs_n, sdi_n, conv_n 755 840 1020 a i ntx0 north 0 transmitter current cs_n, conv_n 1 a i ntx0a north 0 transmitter current sclk_n, sdi_n (base device cs_h = 1) 1 a i ntx0b north 0 transmitter current sclk_n, sdi_n (base device cs_h = 0) 6 8 10 a i srx south 1 receiver threshold sclk_s, cs_s, sdi_s, conv_s 525 620 665 a i srxh south receiver hysteresis sclk_s, cs_s, sdi_s, conv_s 100 200 350 a i stx1 south 1 transmitter current alert_n, fault_s, drdy_s 925 1040 1200 a i stx0 south 0 transmitter current alert_s, fault_s, drdy_s 1 a i stx0a south 0 transmitter current sdo_s (base device cs_h = 1) 1 a i stx0b south 0 transmitter current sdo_s (base device cs_h = 0) 10 20 30 a i nrx north 1 receiver threshold sdo_n, alert_n, fault_n, drdy_n 350 420 580 a i nrxh north receiver hysteresis sdo_n, alert_n, fault_n, drdy_n 100 200 350 a c in input capacitance 15 pf copyright ? 2011, texas instruments incorporated 7 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com host interface typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min typ max unit logic-level output voltage, high; sdo_h, fault_h, v oh c l = 20 pf, i oh < 5 ma (1) 4.5 v ldod v alert_h, drdy logic-level output voltage, low; sdo_h, fault_h, v ol c l = 20 pf, i ol < 5 ma (1) vss 0.5 v alert_h, drdy logic-level input voltage, high; sclk_h, sdi_h, cs_h, v ih 2 5.2 v conv logic-level input voltage, low; sclk_h, sdi_h, cs_h, v il vss 0.8 v conv c in input capacitance sclk_h, sdi_h, cs_h, conv 5 pf i lkg input leakage current sclk_h, sdi_h, cs_h, conv 1 a (1) total simultaneous current drawn from all pins is limited by ldod current to 10 ma. general purpose input/output (gpio) typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min typ max unit v ih logic-level input voltage, high vin v reg50 2 v v il logic-level input voltage, low 0.8 v v oh output high-voltage pullup voltage supplied by external ~100-k resistor v reg50 v v ol logic-level output voltage, low i ol = 1 ma 0.3 v c in input capacitance(1) 5 pf i lkg input leakage current 1 a cell balancing control output (cbx) typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test conditions min typ max unit cb z output impedance 1 v < v cell < 5 v 80 100 120 k v range output v v cn-1 v cn v analog-to-digital converter adc common specifications typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min typ max unit adc_control[adc_on] = 1 5.4 6 6.6 s t conv_start conv high to conversion start (1) (2) (3) adc_control[adc_on] = 0 500 s adc_control[adc_on] = 1 t conv conversion time per selected channel (3) (4) 5.4 6 6.6 s function_confg[adctx]=00 i lkg input leakage current not converting < 10 100 na (1) if adc_control[adc_on] = 0, add 500 s to conversion time to allow adc subsystem to stabilize. this is self-timed by the part. (2) additional 50 ms (por) is required before first conversion after a) initial cell connection; or b) v bat falls below v por . (3) adc specifications valid when device is programmed for 6- s conversion time per channel, func_config[adct1:0] = 01b. (4) plus t conv_start , i.e., if device is programmed for six channel conversions, total time is approximately 6 6 + 6 = 42 s. 8 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 vcn (cell) inputs typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted), function_config[]=01xxxx00b for all test conditions (6- s conversion time selected). parameter test conditions min typ max unit v in input voltage range (1) vcn C vcn C 1, where n = 1 to 6 0 6 v v res voltage resolution (2) 14 bits ~378 v voltage accuracy, (3) total C 10 c t a 50 c, 1.2 v < v in < 4.5 v C 2.5 1 2.5 v acc error, mv C 40 c t a 105 c, 1.2 v < v in < 4.5 v C 5 5 v in = vcn to vcn C 1 r in effective input resistance converting 2 m c in input capacitance (3) converting 1 pf e n noiseslusa086559 v in = 3 v < 250 v rms (1) 0 v may not lie within the range of measured values due to offset voltage limit and device calibration. (2) see text for specific conversion formula. (3) adc is factory trimmed at the conversion speed of ~6 s/channel (func_config[adct1:0] = 01b). use of a different conversion-speed setting may affect measurement accuracy. v bat (v brick ) measurement typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted), function_config[] = 01xxxx00b for all test conditions parameter test condition min typ max unit input voltage range (1) , v in function_config[] = 0101xx00b 0 30 v batn to vss v res voltage resolution (2) 14 bits ~1.831 mv v acc voltage accuracy (3) total error C 80 C 30 20 mv c in input capacitance converting 1 pf r in effective input resistance converting 50 k e n noise < 1.5 mv rms (1) 0 v may not lie within the range of measured values due to offset voltage limit and device calibration. (2) see text for specific conversion formula. (3) adc is factory trimmed at the conversion speed of ~6 s/channel (func_config[adct1:0] = 01b). use of a different conversion-speed setting may affect measurement accuracy. gpai measurement typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted), function_config[] = 0101xx00b for all test conditions parameter test condition min typ max unit input voltage range, (1) v in 0 2.5 v gpai+ to gpai C v res voltage resolution (2) 14 bits ~153 v 0.25 v v in 2.5 v C 7 7 voltage accuracy, (3) v in = v acc mv gpai+ C gpai C v in = 1.25 v, t a = 25 c 2 c in input capacitance converting 40 pf r in effective input resistance converting 50 k e n noise < 150 v rms (1) 0 v may not lie within the range of measured values due to offset voltage limit and device calibration. (2) see text for specific conversion formula. (3) adc is factory trimmed at the conversion speed of ~6 s/channel (func_config[adct1:0] = 01b). use of a different conversion-speed setting may affect measurement accuracy. copyright ? 2011, texas instruments incorporated 9 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com tsn measurement typical values stated where t a = 25 c and bat = 20v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2v to 27v (unless otherwise noted), function_config[]=01xxxx00b for all test conditions parameter test condition min typ max unit v in input voltage range, (1) tsn+ tsn C 0 2.5 v 14 bits, reg50 = 5 v, v res voltage resolution, (2) ~153 v (resolution v reg50 /2 15 ) v acc ratio accuracy, % of input (2) 0.25 v v in 2.4 v C 0.7% 0.2% 0.7% c in input capacitance converting 40 pf r in effective input resistance converting 50 k e n noise < 150 v rms (1) 0 v may not lie within the range of measured values due to offset voltage limit and device calibration. (2) see text for specific conversion formula. thermal shutdown parameter test conditions min typ max unit t sd shutdown threshold bat = 20 v 125 142 156 c t hys recovery hysteresis 8 25 c 10 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 undervoltage lockout (uvlo) and power-on reset (por) typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min nom max unit v uvlo negative-going threshold 5 5.6 v v uvlo_hsy hysteresis 250 375 500 mv uvlo delay delay to locked-out condition v v uvlo min 15 s v por negative-going threshold 4 5 v v por_hsy hysteresis 250 500 750 mv por delay delay to disabled condition v v por min 15 s t rst reset delay time v v por + v por_hsy 40 56 70 ms v delta_rise voltage delta between trip points v uvlo C v por (v bat rising) 0.3 0.4 0.7 v v delta_fall voltage delta between trip points v uvlo C v por (v bat falling) 0.4 0.52 0.7 v battery protection thresholds typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min nom max unit v ovr ov detection threshold range (1) 2 5 v v ovs ov detection threshold program step 50 mv v ovh ov detection hysteresis 50 mv v ova1 ov detection threshold accuracy 3.3 v ov_set 4.5 C 50 0 50 mv v ova2 ov detection threshold accuracy v ov_set < 3.3 or v ov_set > 4.5 C 70 0 70 mv v uvr uv detection threshold range (1) 700 3300 mv v uvs uv detection threshold program step 100 mv v uvh uv detection hysteresis 100 mv v uva uv detection threshold accuracy C 100 0 100 mv v otr ot detection threshold range (2) v reg50 = 5 v 1 2 v vots ot detection threshold program step (2) see (3) v v ota ot detection threshold accuracy (2) t = 40 c to 90 c 0.04 0.05 v v oth ot reset hysteresis t = 40 c to 90 c 8% 12% 15% (1) cov and cuv thresholds must be set such that cov C cuv 300 mv (2) using recommended components. consult table 1 in text for voltage levels used. (3) see table 1 for trip points. copyright ? 2011, texas instruments incorporated 11 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com battery protection delay times typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min nom max unit t ov ov detection delay-time range 0 3200 ms covt [ s/ms] = 0 100 s t ov ov detection delay-time step covt [ s/ms] = 1 100 ms t uv uv detection delay-time range 0 3200 ms cuvt[7] ( s/ms) = 0 100 s t uv uv detection delay-time step cuvt[7] ( s/ms) = 1 100 ms t ot ot detection delay-time range 0 2550 ms t ot ot detection delay-ime step 10 ms ov, uv, and ot detection delay-time t acr cuvt, (covt) 500 s C 12% 0% 10% accuracy (1) v ot or v ov or v uv threshold exceeded by t (detect) protection comparator detection time 100 s 10 mv (1) under double or multiple fault conditions (of a single type), the second or greater fault may have its delay time shortened by up to the step time for the fault. i.e., the second and subsequent cov faults occurring within the delay time period for the first fault may have their delay time shortened by up to 100 s. otp eprom programming characteristics typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min nom max unit v prog programming voltage 6.75 7 7.25 v t prog programming time v bat 20 v 50 ms i prog programming current 10 20 ma 12 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 ac timing characteristics spi data interface typical values stated where t a = 25 c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test condition min typ max unit f sclk sclk frequency (1) 10 250 1000 khz sclk dc sclk_h duty cycle, t (high) / t (sclk) or t (low) / t (sclk) 40% 60% t cs,lead cs_h lead time, cs_ h low to clock 50 sclk/2 ns t cs,lag cs_h lag time. last clock to cs_ h high 10 sclk/2 ns t cs,dly cs_h high to cs_h low (inter-packet delay requirement) 3 s t acc cs_h access time (2) : cs_h low to sdo_h data out 125 250 ns cs_h disable time (2) : cs_h high to sdo_h high t dis 2.5 2.7 s impedance t su,sdi sdi_h input-data setup time 15 ns t hd,sdi sdi_h input-data hold time 10 ns sdo_h output-data valid time t valid,sdo c l 20 pf 75 110 ns sclk_h edge to sdo_h valid (1) maximum sclk frequency is limited by the number of bq76pl536 -q1 devices in the vertical stack. the maximum listed here may not be realizable in systems due to delays and limits imposed by other components including wiring, connectors, pcb material and routing, etc. see text for details. (2) time listed is for single device. figure 3. spi host interface timing vertical communications bus typical values stated where t a = 25 o c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 o c and bat = 7.2 v to 27 v (unless otherwise noted) copyright ? 2011, texas instruments incorporated 13 t cs , lead cs t cs,lag t (sclk ) sclk t (high) t (low) sdi t su,sdi t hd,sdi sdo t acc t valid, sdo t dis t cs _ dly BQ76PL536-Q1 slusab1 C may 2011 www.ti.com vertical communications bus (continued) typical values stated where t a = 25 o c and bat = 20 v, min/max values stated where t a = C 40 ? c to 105 o c and bat = 7.2 v to 27 v (unless otherwise noted) parameter test conditions min typ (1) max unit t hv_sclk propagation delay, sclk_h to host = 0 40 ns sclk_n t vb_sclk propagation delay, sclk_s to host = 1 30 ns sclk_n t hv_sclk propagation delay, cs_h to cs_n host = 0 40 ns t vb_sclk propagation delay, cs_s to cs_n host = 1 30 ns t hv_sdi propagation delay, sdi_h to sdi_n host = 0 40 ns t vb_sdi propagation delay, sdi_s to sdi_n host = 1 30 ns t hv_conv propagation delay, conv_h to host = 0 100 ns conv_n t vb_conv propagation delay, conv_s to host = 1 30 ns conv_n t hv_sdo propagation delay, sdo_n to host = 0 10 ns sdo_h t vb_sdo propagation delay, sdo_n to host = 1 40 ns sdo_s t hv_drdy propagation delay, drdy_n to host = 0 60 ns drdy_h t vb_drdy propagation delay, drdy_n to host = 1 40 ns drdy_s t hv_fault propagation delay, fault_n to host = 0 55 ns fault_h t vb_fault propagation delay, fault_n to host = 1 30 ns fault_s t hv_alert propagation delay, alert_n to host = 0 65 ns alert_h t vb_alert propagation delay, alert_n to host = 1 30 ns alert_s (1) typical values are quoted in place of min/max for design guidance only. actual propagation delay depends heavily on wiring and capacitance in the signal path. these parameters are not tested in production due to these dependencies on system design considerations. analog-to-digital conversion (adc) general features the integrated 14-bit (unsigned) high-speed successive approximation register (sar) analog-to-digital converter uses an integrated band-gap reference voltage (v ref ) for the cell and brick measurements. the adc has a front-end multiplexer for nine inputs C six cells, two temperature sensors, and one general-purpose analog input (gpai). the gpai input can further be multiplexed to measure the brick voltage between the batx pin and vc0 or the voltage between the gpai+ and gpai C pins. the adc and reference are factory trimmed to compensate for gain, offset, and temperature-induced errors for all inputs. the measurement result is not allowed to roll over due to offset error at the top and bottom of the range, i.e., a reading near zero does not underflow to 0x03ff due to offset error, and vice-versa. the converter returns 14 valid unsigned magnitude bits in the following format: < 00xxxxxx xxxxxxxx > each word is returned in big-endian format in a register pair consisting of two adjacent 8-bit registers. the msb of the word is located in the lower-address register of the pair, i.e., data for cell 1 is returned in registers 0x03 and 0x04 as 00xxxxxx xxxxxxxxb. 14 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 3 to 6 series cell configuration when fewer than 6 cells are used, the most-positive cell voltage of the series string should be connected to the bat1/bat2 pins, through the rc input network shown in the reference schematic section. unused vcx inputs should be connected to the next vcx input down until an input connected to a cell is reached C i.e., in a four cell stack, vc6 connects to vc5, which connects to vc4. the internal multiplexer control can be set to scan only the inputs which are connected to cells, thereby speeding up conversions slightly. the multiplexer is controlled by the adc_control[cn2:0] bits. figure 4. connecting < 6 cells (4 shown) cell voltage measurements converting the returned cell measurement value to a dc voltage (in mv) is done using the following formula (all values are in decimal). mv = (reg msb 256 + reg lsb ) 6250 / 16383 example: cell_1 == 3.35 v (3350 mv); after conversion, reg_03 == 0x22; reg_04 == 0x4d 0x22 0x100 + 0x4d = 0x224d (8781.) 8781 6250 / 16,383 = 3349.89 mv 3.35 v gpai or v bat measurements the bq76pl536 -q1 features a differential input to the adc from two external pins, gpai+ and gpai C . the adc gpai result register can be configured (via the function_config[gpai_src] to provide a measurement of the voltage on these two pins, or of the brick voltage present between the batx pins and vc0. in the bq76pl536 -q1 device, the v bat measurement is taken from the batx pin to the vc0 pin, and is a separate input to the adc mux. because this is a separate input to the adc, certain common system faults, such as a broken cell wire, can be easily detected using the bq76pl536 -q1 and simple firmware techniques. copyright ? 2011, texas instruments incorporated 15 0.1 f m 0.1 f m 64 63 bat bat 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vc6 cb6 vc5 cb5 vc4 cb4 vc3 cb3 vc2 cb2 vc1 cb1 vc0 vss agnd vref 1 1 1 k w 1 k w 1 k w 1 k w 1 k w 1 k w 1 0.1 f m 0.1 f m 0.1 f m 10 f m BQ76PL536-Q1 slusab1 C may 2011 www.ti.com the gpai measurement can be configured to use one of two references via function_config[gpai_ref]. either the internal bandgap (v ref ) or reg50 can be selected. when reg50 is selected, the adc returns a ratio of the voltage at the inputs and reg50, removing the need for compensation of the reg50 voltage accuracy or drift when used as a source to excite the sensor. when the device is configured to measure v bat (function_config[gpai_src] = 1), the device selects vref automatically and ignores the function_config[gpai_ref] setting. converting gpai result to voltage to convert the returned gpai measurement value to a voltage using the internal band-gap reference (function_config[gpai_ref] = 1), the following formula is used. mv = (reg msb 256 + reg lsb ) 2500 / 16,383 function_config[] = 0100 xxxxb example: the voltage connected to the gpai inputs == 1.25 v; after conversion, reg_01 == 0x20; reg_02 == 0x00 0x20 0x100 + 0x00 = 0x2000 (8192.) 8192 2500 / 16,383 = 1250 mv converting vbat result to voltage to convert the returned v bat measurement value to a voltage, the following formula is used. v = (reg msb 256 + reg lsb ) 33.333 / 2 14 (33.333 6.25 / 0.1875) function_config[] = 0101 xxxxb example: the sum of the series cells connected to vc6 C vc0 == 20.295 v; after conversion, reg_01 == 0x26; reg_02 == 0xf7 0x26 0x100 + 0xf7 = 0x26f7 (9975.) 9975 33.333 / 16,383 = 20.295 v temperature measurement the bq76pl536 -q1 can measure the voltage ts1+, ts1 C and ts2+, ts2 C differential inputs using the adc. these inputs are typically driven by an external thermistor/resistor divider network. the tsn inputs use the reg50 output divided down and internally connected as the adc reference during conversions. this produces a ratiometric result and eliminates the need for compensation or correction of the reg50 voltage drift when used to drive the temperature sensors. the reg50 reference allows an approximate 2.5-v full-scale input at the tsn inputs. the final reading is limited between 0 and 16,383, corresponding to an external ratio of 0 to 0.5. two control bits are required for the adc to convert the tsn input voltages successfully. adc_control[tsn] is set to cause the adc to convert the tsn channel on the next requested conversion cycle. io_control[tsn] is set to cause the fet switch connecting the tsn C input to vss to close, completing the circuit of the voltage divider. the io_control[] bits should only be set as needed to conserve power; at high temperatures, thermistor excitation current may be relatively high. external temperature sensor support (ts1+, ts1 C and ts2+, ts2 C ) the device is intended for use with a nominal 10 k at 25 o c ntc external thermistor (at103 equivalent) such as the panasonic ert-j1vg103fa, a 1% device. a suitable external resistor-capacitor network should be connected to position the response of the thermistor within the range of interest. this is typically r t = 1.47 k and r b = 1.82 k (1%) as shown in figure 5 . a parallel bypass capacitor in the range 1 nf to 47 nf placed across the thermistor should be added to reduce noise coupled into the measurement system. the response time delay created by this network should be considered when enabling the respective ts input prior to conversion and setting the ot delay timer. see figure 5 for details. 16 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 figure 5. thermistor connection converting tsn result to voltage (ratio) to convert the returned tsn measurement value to a ratio, r ts = v ts :reg50, the following formula s are used. the setting function_config[] = 0100 xxxxb is assumed. note that the offset and gain correction are slightly different for each channel. adc behavior: count = (v tsn / reg50 scalar) C offset ts1: r ts1 = ((temperature1_h 256 + temperature1_l) + 2) / 33,046 ts2: r ts2 = ((temperature2_h 256 + temperature2_l) + 9) / 33,068 example: the voltage connected to the ts 1 inputs (ts 1+ C ts 1 C ) == 0.66 1 v; v reg50 5 v nominal after conversion, reg msb == 0x11; reg lsb == 0x1 6 actual_count = 0x11 0x100 + 0x1 6 = 0x111 6 (437 4.) (4374 + 2) / 33,046 = 0.1324 (ratio of tsn inputs to reg50) 0.132 4 reg50 = 0.66 2 v adc band-gap voltage reference the adc and protection subsystems use separate and independent internal voltage references. the adc bandgap (v ref ) is nominally 2.5 v. the reference is temperature-compensated and stable. the internal reference is brought out to the vref pin for bypassing. a high quality 10- f capacitor should be connected between the vref and agnd pins, in very close physical proximity to the device pins, using short track lengths to minimize the effects of track inductance on signal quality. the agnd pin should be connected to vss. device vss connections should be brought to a single point close to the ic to minimize layout-induced errors. the device tab should also be connected to this point, and is a convenient common vss location. the internal vref should not be used externally to the device by user circuits. conversion control convert start two methods are available to start a conversion cycle. the conv_h pin may be asserted, or firmware may set the convert_ctrl[conv] bit. copyright ? 2011, texas instruments incorporated 17 47 nf r th r t r b reg50 ts+ tsC r b th@40c th@90c = 0.4 (r C r ) r t = r th@ 40c C 2r th @90c C r b BQ76PL536-Q1 slusab1 C may 2011 www.ti.com hardware start a single interface pin (conv_h) is used for conversion-start control by the host. a conversion cycle is started by a hardware signal when conv_h is transitioned low-to-high by the host. the host should hold this state until the conversion cycle is complete to avoid erroneous edges causing a conversion start when the present conversion is not complete. the signal is simultaneously sent to the higher device in the stack by the assertion of the conv_n signal. the bq76pl536 -q1 automatically sequences through the series of measurements enabled via the adc_control[] register after a convert-start signal is received from either the register bit or the hardware pin. if the conv_h pin is used in the design, it must be maintained in a default low state (~0 v) to allow use of the adc_convert[conv] bit to trigger adc conversions. if the conv pin is kept high, the adc_convert[conv] bit does not function, and device current consumption is increased by the signaling current, ~900 a. if the conv_h pin is not used by the user s design, the pin may be left floating; the internal current sink to vss maintains proper bias. firmware start the convert_ctrl[conv] bit is also used to initiate a conversion by writing a 1 to the bit. it is automatically reset at the end of a conversion cycle. the bit may only be written to 1; the ic always resets it to 0. the broadcast form of packet is recommended to start all device conversions simultaneously. designer note: the external conv_h (conv_s) pin must be held in the de-asserted (=0) state to allow the conv register bit to initiate conversions. an internal pulldown is provided on the pin to maintain this state. data ready the bq76pl536 -q1 signals that data is ready when the last conversion data has been stored to the associated data result register by asserting the drdy_s pin (drdy_h if host = 0) if the drdy_n pin is also asserted. drdy_s (drdy_h) signals are cleared on the next rising edge of conv_h. the device_status[drdy] bit indicates the state of the drdy_n pin. designer note: the drdy_s pins remain asserted during sleep, leading to extra current consumption. as a workaround, user designs should read the last result of a conversion before placing the device in sleep. adc channel selection the adc_control register can be configured as follows: measurement adc_control vcell1 cell_sel = 0x00 vcell1, vcell2 cell_sel = 0x01 vcell1, vcell2, vcell3 cell_sel = 0x02 vcell1, vcell2, vcell3, vcell4 cell_sel = 0x03 vcell1, vcell2, vcell3, vcell4, vcell5 cell_sel = 0x04 vcell1, vcell2, vcell3, vcell4, vcell5, vcell6 cell_sel = 0x05 external thermistor input 1 ts1 = 1 external thermistor input 2 ts2 = 1 general-purpose analog input gpai = 1 conversion time control the adc can be configured to adjust the conversion time to meet system requirements. the default conversion time is approximately 3 s (with adc pre-configured to be on by setting the adc_control[adc_on] bit). this can be adjusted to approximately 3, 6, 12, or 24 s/channel by changing the value in the function_config[] register. the 6- s setting (function_config[adct1:0] = 01b) is recommended for best results over temperature. 18 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 automatic vs manual control the adc_control[adc_on] bit controls powering up the adc section and the main bandgap reference. if the bit is set to 1, the internal circuits are powered on, and current consumption by the part increases. conversions begin immediately on command. the host cpu should wait > 500 s before initiating the first conversion after setting this bit. if the adc_on bit is false, an additional 500 s is required to stabilize the reference before conversions begin. in this automatic mode, power consumption is greatly reduced. automatic mode is only available for the 3- s conversion timing. when the 6-, 12-, or 24- s timing is selected, manual control of the adc_on bit must be used to avoid locking up the internal state machine, which then requires a broadcast_reset command be sent or a por to correct. if the sampling interval (time between conversions) used is less than ~10 ms, manual mode should be selected to avoid shifting the voltage reference, leading to inaccuracy in the measurements. adc application notes anti-aliasing filter an anti-aliasing filter is required for each vcn input vc6 C vc2, consisting of a 1-k , 1% series resistor and 100-nf capacitor. the same filter is used, but with a 1- f capacitor for the vc1 and vc0 sections. good-quality components should be used. a 1% resistor is recommended, because the resistor creates a small error by forming a voltage divider with the input impedance of the part. the part is factory-trimmed to compensate for the error introduced by the filter. using the 6- s conversion setting 1. the conversion time is adjusted from 3 s/channel to 6 s/channel. this extends the total time to convert all cell voltages from 21 s (6 3 s + 3 s) to 42 s (6 6 s + 6 s). to convert all cell voltages, plus the brick voltage, plus the two temperature inputs requires 60 s (9 6 s + 6 s). 2. the adc_ctrl[adc_on] bit is set to 1 for conversions. the adc_ctrl[] register is located at address 0x30. the conversion time is controlled by the function_config[] register at address 0x40. two bits, adct0, adct1 set the time. function_config register (0x40) 7 6 5 4 3 2 1 0 adct[1] adct[0] gpai_ref gpai_src cn[1] cn[0] - - the function_config sets the default configuration for special features of the device. [7..6] (adct[0,1]): these bits set the conversion timing of the adc measurement. adct[1] adct[0] ~conversion time ( s) 0 0 3 0 1 6 1 0 12 1 1 24 a design issue in the device requires that any time the adct[1:0] bits are not equal to 0, the adc_on bit must be set to 1 before initiating a conversion cycle. ti recommends setting the bit to 1 during battery operations when conversions are to be made (it may be left on). the bit can be turned off when conversions are not active, i.e., during the key-off time. when the bit is turned on, the hardware enforces a 500- s 5% wait before conversions are permitted. user firmware should wait the minimum 500 s before requesting a conversion start after adc_on = 1. copyright ? 2011, texas instruments incorporated 19 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com note if a conversion cycle is inadvertedly started while (adct[1:0] 0 < and > adc_on = 0), the device appears to lock up and stop working. to correct this behavior, send a device reset command (write 0xa5 to register 0x3c) followed by any customer-specific register initialization. the reset command also resets the device address to 0x00, making it necessary to reassign addresses to all devices in the stack. the bit may be turned on and left on, or dynamically manipulated at each conversion depending on user firmware requirements. ti recommends programming the otp register to set the conversion rate permanently. this procedure is described in the data sheet for the device. a typical value for function_config[] register 0x40 is 0x50. see the function_config register (0x40) section for further details of the other bit functions. procedure: otp eprom is pre-programmed to 6 s (0x40 = 0101 xx00b): 1. prior to any conversion: write adc_config[adc_on] = 1 (0x30 = 01xx xxxxb) note: the typical setting used to convert all inputs is adc_control[] = 0111 1101b. alternate method - use shadow ram feature (eprom 0x40 programmed value is don t care): the shadow ram feature allows temporarily overwriting eprom contents. at reset, group3 ram registers are loaded from otp eprom. the device always uses the contents of the ram register internally to control the device. the ram register may be subsequently overwritten with a new value to modify the device defaults programmed in eprom. the new value is valid until the next device reset. this example assumes that all inputs are converted. 1. setup for 6- s/ch conversion time: write shdw_ctrl[] = 0x35 (register 0x3a = 0x35) to enable the write to function_config[]. immediately followed by: write function_config[] = 0x50 (register 0x40 = 0x50) 2. prior to any conversion: write adc_ctrl[] = 0x7d (register 0x30 = 0x7d) wait > 1 ms before converting after setting adc_on = 1 in the previous step. 3. converting: conversions are now initiated normally, using the conv_h pin or the convert[conv] register bit. note: power may be significantly reduced by setting the bit adc_on = 0. secondary protection the bq76pl536 -q1 integrates dedicated overvoltage and undervoltage fault detection for each cell and two overtemperature fault detection inputs for each device. the protection circuits use a separate band-gap reference from the adc system and operate independently. the protector also uses separate i/o pins from the main communications bus, and therefore is capable of signaling faults in hardware without intervention from the host cpu. protector functionality when a fault state is detected, the respective fault flag in the fault_status[] or alert_status[] registers is set. all flags in the fault and alert registers are then ored into the device_status[] fault and alert bits. the fault and alert bits in device_status[] in turn cause the hardware fault_s or alert_s pin to be set. the bits in device_status[] and the hardware pins are latched until reset by the host via spi command, ensuring that the host cpu does not miss an event. 20 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 a separate timer is provided for each fault source (cell overvoltage, cell undervoltage, overtemperature) to prevent false alarms. each timer is programmable from 100 s to more than 3 s. the timers may also be disabled, which causes fault conditions to be sensed immediately and not latched. the clearing of the fault or alert flag (and pin) occurs when the respective flag is written to a 1, which also restarts the respective fault timer. this also clears the fault_s (_h) or alert_s (_h) pin. if the actual fault remains present, the fault (alert) pin is again asserted at the expiration of the timer. this cycle repeats until the cause of the fault is removed. on exit from the sleep state, the cov, cuv, and ot fault comparators are disabled for approximately 200 s to allow internal circuitry to stabilize and prevent false error condition detection. using the protector functions with 3-5 cells the ov/uv condition can be ignored for unused channels by setting the function_config[cnx] bits to the maximum number of cells connected to the device. if fewer than 6 cells are configured, the corresponding ov/uv faults are ignored. for example, if the function_config[] bits are set to xxxx 1000, then the ov/uv comparators are disabled for cells 5 and 6. correct setting of this register prevents spurious false alarms. cell overvoltage fault detection (cov) when the voltage across a cell exceeds the programmed cov threshold for a period of time greater than set in the cov timer (covt), the cov_fault[] flag for that cell is set. the bits in cov_fault[] are then ored into the fault[cov] flag, which is then ored into the device_status[fault] flag, which causes the fault_s (_h) pin also to be asserted. the cov flag is latched unless covt is programmed to 0, in which case the flag follows the fault condition. care should be taken when using this setting to avoid chatter of the fault status. to reset the fault flag, first remove the source of the fault (i.e., the overvoltage condition) and then write a 1 to fault[cov], followed by a 0 to fault[cov]. the voltage trip point is set in the config_cov register. set points are spaced every 50 mv. hysteresis is provided to avoid chatter of the fault sensing. the filter delay time is set in the config_covt[] register to prevent false alarms. a start-up deglitch circuit is applied to the timers to prevent false triggering. the deglitch time is 0 C 50 s, and introduces a small error in the timing for short times. for both covt and cuvt, this can cause an error greater than the 10% maximum specified for delays < 500 s. figure 6. cov fault simplified logic tree copyright ? 2011, texas instruments incorporated 21 - - vc6 vc5 vc4 vc3 vc2 vc1 cov_fault - - i_ fault force por crc cuv cov fault ar fault alert - ecc_ cor uvlo cbt drdy status covt filter analog translation fault _s fault _h fault _n latch +C cov comparator (one per cell) + C protector reference config_cov[] vc6 level shifter trip setpoint vss BQ76PL536-Q1 slusab1 C may 2011 www.ti.com cell undervoltage fault detection (cuv) cell undervoltage detection operates in a similar manner to the cov protection. when the voltage across a cell falls below the programmed cuv threshold (config_cuv[]) for a period of time greater than cuvt (config_cuvt[]), the cuv_fault[] flag for that cell is set. the bits in cuv_fault[] are then ored into the fault[cuv] flag, which is then ored into the device_status[fault] flag, which causes the fault_s (_h) pin also to be asserted. the cuv flag is latched unless cuvt is programmed to 0, in which case the flag follows the fault condition. care should be taken when using this setting to avoid chatter of the fault status. to reset the fault flag, first remove the source of the fault (i.e., the overvoltage condition) and then write a 1 to fault[cuv], followed by a 0 to fault[cuv]. overtemperature detection when the temperature input ts1 or ts2 exceeds the programmed ot1 or ot2 threshold (config_ot[]) for a period of time greater than ott (config_ott[]) the alert_status[ot1, ot2] flag is set. the alert[] flags are then ored into the device_status[alert] flag, and the alert_s (_h) pin is also asserted. the ot flag is latched unless ott is programmed to 0, in which case the flag follows the fault condition. care should be taken when using this setting to avoid chatter of the fault status. to reset the fault flag, first remove the source of the alert (i.e., the overtemperature condition) and then write a 1 to alert[otn], followed by a 0 to fault[otn]. figure 7. simplified overtemperature detection schematic as shown in the drawing above, the ot thresholds are detectable in 11 steps representing approximately 5 c divisions when a thermistor and gain/offset setting resistors are chosen using the formula in the external temperature sensor support (ts1+, ts1 C and ts2+, ts2 C ) section. a disabled setting is also available. this results in an adjustment range from approximately 40 c to 90 c, but the range center can be moved by modifying the r t value. the steps are spaced in a non-linear fashion to correspond to typical thermistor response curves. typical accuracy of a few degrees c or better can be achieved (with no additional calibration requirements) by careful selection of the thermistor and resistors. each input sensor can be adjusted independently via separate registers config_ot1[] and config_ot2[]. the two temperature setpoints share a common filter delay set in the config_ott[] register. a setting of 0 in the config_ott[] register causes the fault sensing to be both instantaneous and not latched. all other settings provide a latched alert state. 22 copyright ? 2011, texas instruments incorporated reg50 c f r th r t r b reg50 ts+ tsC io_ctrl[tsn] alert[otn] pin boundary to adc mux +C delay filter comparator config_ot[] selector config_ott[] 11 1 config_ot[]?0 vss +C protector reference 5v ldo (user) to cov-cuv circuits v bat BQ76PL536-Q1 www.ti.com slusab1 C may 2011 ratiometric sensing the ot protector circuits use ratiometric inputs to sense fault conditions. the reg50 output is applied internally to the divider which forms the reference voltages used by the comparator circuit. it is also used externally as the excitation source for the temperature sensor. this allows the reg50 output to vary over time or temperature (within data-sheet limits) and have virtually no effect on the correct operation of the circuit. any change seen by the sensor is also seen by the divider, and therefore, changes proportionally. although it is valid to represent the trip setpoints as voltages if you assume that reg50 is at exactly 5 v, in practice, this is not the case. in the chart included in the next section, the correct ratios [r b /(r b + r t + r th )] are shown, along with the equivalent voltage points when reg50 is assumed to be 5 v. table 1. overtemperature trip setpoints ot thresholds config_ot t nom c v ts ratio set v ts ratio clear v set (1) v clear (1) 0 disabled disabled disabled disabled disabled 1 40 0.2000 0.1766 1.000 0.883 2 45 0.2244 0.2000 1.122 1.000 3 50 0.2488 0.2270 1.244 1.135 4 55 0.2712 0.2498 1.356 1.249 5 60 0.2956 0.2750 1.478 1.375 6 65 0.3156 0.2956 1.578 1.478 7 70 0.3356 0.3162 1.678 1.581 8 75 0.3556 0.3368 1.778 1.684 9 80 0.3712 0.3528 1.856 1.764 10 85 0.3866 0.3688 1.933 1.844 11 90 0.4000 0.3824 2.000 1.912 (1) assumes reg50 = 5.000 v thermistor power to minimize power consumption, the thermistors are not powered on by default. two bits are provided in io_control[] to control powering the thermistors, ts1 and ts2. the tsn C input is only connected to vss when the corresponding bit is set. the user firmware must set these bits to 1 to enable both temperature measurement and the secondary protector functions. when the thermistor functions are not in use, the bits may be programmed to 0 to remove current through the thermistor circuits. thermistor input conditioning a filter capacitor is recommended to minimize noise in to the adc and protector. the designer should insure that the filter capacitor has sufficient time to charge before reading the thermistors. the config_ott[] value should also be set to > 5t, the time delay introduced by the rc network comprising c f , r th , r t , and r b , to avoid false triggering of the protector function and alert signal when the ts1 and/or ts2 bits are set to 1 and the inputs enabled. on exit from the sleep state, the ot fault comparators are disabled for approximately 200 s to allow internal circuitry to stabilize and prevent false error-condition detection. fault and alert behavior when the fault_n pin is asserted by the next higher bq76pl536 -q1 in the stack, then the fault_s is also asserted, thereby passing the signal down the array of stacked devices if they are present. fault_n should always be connected to the fault_s of the next higher device in the stack. if no higher device exists, it should be tied to v bat of this bq76pl536 -q1, either directly or via a pullup resistor ~10 k to 1 m . the fault_x pins are active-high C current flows when asserted. the alert_x pins behave in a similar manner. if the fault_n pin of the base device (hsel = 0) becomes asserted, it asserts its fault_h signal to the host microcontroller. this signal chain may be used to create an interrupt to the cpu, or drive other compatible logic or i/o directly. copyright ? 2011, texas instruments incorporated 23 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com table 2. fault detection summary signaling fault detection pin device_status x_status bit set bit set hsel = 1 hsel = 0 eprom double bit ecc logic fault detected fault_s fault_h fault fault_status[i_fault] error force user set force bit fault_s fault_h fault fault_status[force] por power-on reset occurred fault_s fault_h fault fault_status[por] crc crc fail on received packet fault_s fault_h fault fault_status[crc] cuv v cx < v uv for t uv fault_s fault_h fault fault_status[cuv] cov v cx > v ov for t ov fault_s fault_h fault fault_status[cov] ar address (0x01 0x3e) alert_s alert_h alert alert_status[ar] protected-register parity not even in protected alert_s alert_h alert alert_status[parity] parity error register eprom single-bit ecc logic fault detected and alert_s alert_h alert alert_status[ecc_cor] error corrected force user set force bit alert_s alert_h alert alert_status[force] die temperature thermal shutdown alert_s alert_h alert alert_status[tsd] tsd threshold sleep ic exited sleep mode alert_s alert_h alert alert_status[sleep] ot2 v ts2 > v ot for t ot alert_s alert_h alert alert_status[ot2] ot1 v ts1 > v ot for t ot alert_s alert_h alert alert_status[ot1] fault recovery procedure when any error flag in device_status[], fault_status[], or alert_status[] is set and latched, the state can only be cleared by host communication via spi. writing to the respective fault_status or alert_status register bit with a 1 clears the latch for that bit. the exceptions are the two force bits, which are cleared by writing a 0 to the bit. the fault_status[] and alert_status[] register bits are read-only, with the exception of the force bit, which may be directly written to either a 1 or 0. secondary protector built-in self-test features the secondary protector functions have built-in test for verifying the connections through the signal chain of ics in the stack back to the host cpu. this verifies the wiring, connections, and signal path through the ics by forcing a current through the signal path. to implement this feature, host firmware should set the fault[force] or alert[force] bit in the top-most device in the stack. the device asserts the associated pin on the south interface, and it propagates down the stack, back to the base device. the base device in turn asserts the fault_h (alert_h) pin to the host, allowing the host to check for the received signal and thereby verify correct operation. cell balancing the bq76pl536 -q1 has six dedicated outputs (cb1 cb6) that can be used to control external n-fets as part of a cell balancing system. the implementation of appropriate algorithms is controlled by the system host. the cb_ctrl[cbal1 C 6] bits control the state of each of the outputs. the outputs are copied from the bit state of the cb_ctrl register, i.e., a 1 in this register activates the external balance fet by placing a high on the associated pin. the cbx pins switch between approximately the positive and negative voltages of the cell across which the external fet is connected. this allows the use of a small, low-cost n-fet in series with a power resistor to provide cell balancing,. 24 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 cell balance control safety timer the cbx outputs are cleared when the internal safety timer expires. the internal safety timer (cb_time) value is programmed in units of seconds or minutes (range set by cb_ctrl bit 7) with an accuracy of 10%. the timer begins when any cb_ctrl bit changes from 0 to 1. the timer is reset if all cb_ctrl bits are modified by the host from 1 to 0, or by expiration of the timing period. the timing begins counting the programmed period from start each time the cb_ctrl[] register is programmed from a zero to a non-zero value in the lower six bits. in example, if the cb_time[] is set for 30 s, then one or more bits are set in the cb_ctrl[] register to balance the corresponding cells; then after 10 s the user firmware sets cb_ctrl[] to 0x00, takes a measurement, then reprograms cb_ctrl[] with the same or new bit pattern, the timer begins counting 30 s again before expiring and disabling balancing. this restart occurs each time the cb_ctrl bits are set to a non-zero value. if this is done at a greater rate than the balancing period for which timer cb_time[] is set, balancing is effectively never disabled C until the timer is either allowed to expire without changing the cb_ctrl[] register to a non-zero value, or the cb_ctrl[] register is set to zero by the user firmware. if the cb_ctrl[] register is not manipulated from zero to non-zero while the timer is running, the timer expires as expected. alterations of the value from a non-zero to a different non-zero value do not restart the timer (i.e., from 0x02 to 0x03, etc). while the timer is running, the host may set or reset any bit in the cb_ctrl[] register at any time, and the cbx output follows the bit. the host may re-program the timer at any time. the timer must always be programmed to allow the cbx outputs to be asserted. while the timer is non-zero, the cb_ctrl[] settings are reflected at the outputs. during periods when the timer is actively running (not expired), then device_status[cbt] is set. other features and functions internal voltage regulators the bq76pl536 -q1 derives power from the bat pin using several internal low dropout (ldo) voltage regulators. there are separate ldos for internal analog circuits (5 v at ldoa), digital circuits (5 v at ldod1 and ldod2), and external, user circuits (5 v at reg50). the bat pin should be connected to the most-positive cell input from cell 3, 4, 5, or 6, depending on the number of cells connected. locate filter capacitors as close to the ic as possible. the internal ldos and internal v ref should not be used to power external circuitry, with the exception that ldodx should be used to source power to any external pullup resistors. internal 5-v analog supply the internal analog supply should be bypassed at the ldoa pin with a good-quality, low-esr, 2.2- f ceramic capacitor. internal 5-v digital supply the internal digital supply should be bypassed at the ldod1(2) pin with a good-quality, low-esr, 2.2- f ceramic capacitor. the two pins are connected internally and provided to enhance single-pin failure-mode fault tolerance. they should also be connected together externally. designer note: because the ldodx inputs are pulled briefly to ~7 v during programming, the ldodx pins should not be used as sources for pullups to 5-v digital pins, such as hsel and spi(bus)_h connected pins. use vreg50 instead, unless all programming is completed prior to mounting on the application pcb, in which case ldodx is a good choice. low-dropout regulator (reg50) the bq76pl536 -q1 has a low-dropout (ldo) regulator provided to power the thermistors and other external circuitry. the input for this regulator is v bat . the output of reg50 is typically 5 v. a minimum 2.2- f capacitor is required for stable operation. the output is internally current-limited. the output is reduced to near zero if excess current is drawn, causing die temperatures to rise to unacceptable levels. the 2.2- f output capacitor is required whether reg50 is used in the design or not. copyright ? 2011, texas instruments incorporated 25 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com reg50 is disabled in sleep mode, and may be turned off under thermal-shutdown conditions, and therefore should not be used as a pullup source for terminating device pins where required. auxiliary power output (aux) the bq76pl536 -q1 provides an approximately 1-ma auxiliary power output that is controlled via io_control[aux]. this output is taken directly from reg50. the current drawn from this pin must be included in the reg50 current-limit budget by the designer. undervoltage lockout and power-on reset the device incorporates two comparators to detect low v bat conditions. the first detects low voltage where some device digital operations are still available. the second, (por) detects a voltage below which device operation is not ensured. uvlo when the uvlo threshold voltage is sensed for a period uvlo delay , the device is no longer able to make accurate analog measurements and conversions. the adc, cell-balancing and fault-detection circuitry are disabled. the digital circuitry, including host cpu and vertical communications between ics, is fully functional. register contents are preserved with the exception that cb_ctrl is set to 0, and the uvlo bit is set in device_status[]. power-on reset (por) when the por voltage threshold or lower is sensed for a period uvlo delay , the device is no longer able to function reliably. the device is disabled, including all fault-detection circuitry, host spi communications, vertical communications, etc. after the voltage rises above the hysteresis limit longer than the delay time, the device exits the reset state, with all registers set to default conditions. the fault_status[por] bit is set and latched until reset by the host. the device no longer has a valid address (device_address[ar] = 0, address_control[] = 0). the device should be reprogrammed with a valid address, and any registers re-written if non-default values are desired. reset command the bq76pl536 -q1 can also be reset by writing the reset code (0xa5) to the reset register. all devices respond to a broadcast reset command regardless of their current assigned address. the result is identical to a por with the exception that the normal por period is reduced to several hundred microseconds. thermal shutdown (tsd) the bq76pl536 -q1 contains an integrated thermal shutdown circuit whose sensor is located near the reg50 ldo and has a threshold of t sd . when triggered, the reg50 regulator reduces its output voltage to zero, and the adc is turned off to conserve power. the thermal shutdown circuit has a built-in hysteresis that delays recovery until the die has cooled slightly. when the thermal shutdown is active, the device_status[tsd] bit is set. the io_control[sleep] and alert[sleep] bits also become set to reduce power consumption. warning the secondary protector settings are disabled in the tsd state. caution temperature measurement and monitoring do not function due to loss of power if the thermistors are powered from the reg50 or aux pins and tsd occurs. protection-dependent schemes implemented by the designer which depend on the reg50 voltage also may not function as a result of loss of the reg50 output. 26 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 gpio the bq76pl536 -q1 includes a general-purpose input/output pin controlled by the io_control[gpio_out] bit. the state of this bit is reflected on the pin. to use the pin as an input, program gpio_out to a 1, and then read the io_control[gpio_in] bit. a pullup (10 k C 1 m , typ.) is required on this pin if used as an input. if the pullup is not included in the design, system firmware must program a 0 in io_control[gpio_out] to prevent excess current draw from the floating input. use of a pullup is recommended in all designs to prevent an unintentional increase in current draw. sleep functionality the bq76pl536 -q1 provides the host a mechanism to put the part into a low-power sleep state by setting the io_control[sleep] bit. when this bit is set/reset, the following actions occur: sleep state entry (bit set) if a conversion is in progress, the device waits for it to complete, then sets drdy true (high). the device sets the alert_status[sleep] bit, which in turn causes the alert pin to be asserted. the device gates off all other sources of fault or alert except alert[sleep]. the existing state of the fault and alert registers is preserved. the host should service and reset the alert generated by the sleep bit being set to minimize sleep state current draw by writing a 1 to alert[sleep] followed by a 0 to alert[sleep]. the alert north-south signal chain can draw up to ~1 ma of current when active, so this alert source should be cleared prior to the host entering the sleep state of its own. this signaling is provided to notify the host that the unmonitored/unprotected state is being entered. the reg50 ldo is shut down and the output is allowed to float. the adc, its reference, and clocks are disabled. the cov, cuv, and ot circuits are disabled, and their band-gap reference shut off. note that this effectively removes protection and monitoring from the cells; the designer should take the necessary design steps and verifications to ensure the cells cannot be put into an unsafe condition by other parts of the system or usage characteristics. io_control[ts1(2)] bits are not modified. the host must also set these bits to zero to minimize current draw of the thermistors themselves. spi communications are preserved; all registers may be read or written. sleep state exit (bit reset) vreg50 operation is restored. cov, cuv, ot circuits are re-enabled. the adc circuitry returns to its former state. note that there is a warm-up delay associated with the adc enable, the same delay as specified for enabling from a cold start. the fault and alert registers are restored to their pre-sleep state. if a fault or alert condition was present prior to sleep, the fault or alert pin is immediately asserted. io_control[ts1(2)] should be set by the host if the ot function or temperature measurement functions are desired. communications spi communications C device to host device-to-host (d2h) mode is provided on the spi interface pins for connection to a local host microcontroller, logic, etc. d2h communications operate in voltage mode as a standard spi interface for ease of connection to the outside world from the bq76pl536 -q1 device. standard ttl-compatible logic levels are presented. all relevant spi timing and performance parameters are met by this interface. the host interface operates in spi mode 1, where cpol = 0 and cpha = 1. the spi clock is normally low; data changes on rising edges, and is sampled on the falling edge. all transfers are msb-first. copyright ? 2011, texas instruments incorporated 27 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com the pins of the base ic (only) in a stack should have the sclk_h and sdi_h pins terminated with pullups to minimize current draw of the part if the host ever enters a state where the pins are not driven, i.e., held in the high-impedance state by the host. in non-base devices, the _h pins are forced to be all outputs driven low when the hsel pin is high. in non-base devices, all _h pins should remain unconnected. the cs_h has a pullup resistor of approximately 100 k . sdo_h is a 3-state output and is terminated with a weak pullup. designer note: when v bat is at or below the uvlo trip point voltage, the internal ldo which supplies the xxxx_h host spi communications pins (vlodx) begins to fall out of regulation. the output high voltage on the xxxx_h pins falls off with the ldo voltage in an approximately linear manner until at the por voltage trip point it is reduced to approximately 3.5 v. this action is not tested in production. application notes on the host spi interface pin states the cs_h pin is active-low. the host asserts the pin to a logic zero to initiate communications. the cs pin should remain low until the end of the current packet. when the cs_h pin is asserted, the spi receiver and interface of the device are reset and resynchronized. this action ensures that a slave device that has lost synchronization during a previous transmission or as the result of noise on the bus does not remain permanently hung. cs_h must be driven false (high) between packets; see ac timing characteristics for timing details. device-to-device vertical bus (vbus) interface device-to-device (d2d) communications makes use of a unique, current-mode interface which provides common-mode voltage isolation between successive bq76pl536 -q1s. this vertical bus (vbus) is found on the _n and corresponding _s pins. it provides high-speed i/o for both the spi bus and the direct i/o pins conv and drdy. the current-mode interface minimizes the effects of wiring capacitance on the interface speed. the _s (south-facing) pins connect to the next-lower device (operating at a lower potential) in the stack of bq76pl536 -q1s. the _n (north facing) pins connect to the next-higher device. the pins cannot be swapped; _s always points south, and _n always point north. the _s and _n pins are interconnected to the pin with the same name, but opposite suffix. all pins operate within the voltages present at the bat and vss pins. use caution; these pins may be several hundred volts above system ground, depending on their position in the stack. designer note: north (_n) pins of the top, most-positive device in the stack should be connected to the bat1(2) pins of the device for correct operation of the string. south (_s) pins of the lowest, most-negative device in the stack should be connected to vss of the device. the maximum sclk frequency is limited by the number of devices in the vertical stack and other factors. each device imposes an approximately 30-ns delay on the round trip communications speed, i.e., from sclk rising (an input to all devices) to the sdo pin transitioning requires ~30 ns per device. the designer must add to this the delay caused by the pcb trace (in turn determined by the material and layout), any connectors in series with the connection, and any other wiring or cabling between devices in the system. to maximize speed, these other system components should be carefully selected to minimize delays and other detrimental effects on signal quality. wiring and connectors should receive special attention to their transmission line characteristics. other factors which should be considered are clock duty cycle, clock jitter, temperature effects on clock and system components, user-selected drive level for the level-shift interface, and desired design margin. the vbus spi interface is placed in a low-power mode when cs_h is not asserted on the base device. the cs_n/s pins are asserted by a logic high on the vertical interface bus (logically inverted from cs_h). this creates a default vbus cs condition of logic low, reducing current consumption to a minimum. to reduce power consumption of the spi interface to a minimum, the sclk_h and sdi_h should be maintained at a logic low (de-asserted) while cs_h is asserted (low). most spi buses are operated this way by microcontrollers. the vbus versions of these signals are not inverted from the host interface. the device also de-asserts by default the sdo_n/s pins to minimize power consumption. 28 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 packet formats data read packet when the bq76pl536 -q1 is selected (cs_s [cs_h for first device] is active and the bq76pl536 -q1 has been addressed) and read request has been initiated, then the data is transmitted on the sdo_s pin to the sdo_n pin of the next device down the stack. this continues to the first device in the stack, where the data in from the sdo_n pin is transmitted to the host via the sdo_h pin. the device supplying the read data generates a crc as the last byte sent. figure 8. read packet format figure 9. read packet detail data write packet when the bq76pl536 -q1 is selected (cs_s is active and the bq76pl536 -q1 has been addressed) and a write request has been initiated, the bq76pl536 -q1 receives data through the sdi_s pin, which is connected to the sdo_n of the lower device. for the first device in the stack, the data is input to the sdi_h pin from the host, and transmitted up the stack on the sdi_s pin to the sdi_n pin of the next higher device. if enabled, the device checks the crc, which it expects as the last byte sent. if the crc is valid, no action is taken. if the crc is invalid or missing, the device asserts the alert_s signal to the next lower device, which ripples down the stack to the alert_h pin on the lowest device. the host should then take action to clear the condition. unused or undefined register bits should be written as zeros. figure 10. write packet format copyright ? 2011, texas instruments incorporated 29 start reg address 0 device address 0 read length n read data 1 r/w read data n crc read packet cs assertion dev addr cs 1 byte time reg addr wrt data crc dev addr reg addr start of next packet sdi ... dev addr 1 byte time reg addr cnt = n 0x00 0x00 0x00 0x00 read n... crc read 1 read 2 n + 1 placeholder bytes cs sdi sdo 0x00 0x00 0x00 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com figure 11. write packet detail broadcast writes the bq76pl536 -q1 supports broadcasting single register writes to all devices. a write to device address 0x3f is recognized by all devices on the bus with a valid address, and permits efficient simultaneous configuration of all registers in the stack of devices. this also permits synchronizing all adc conversions by a firmware command sent to the convert_ctrl[] register as an alternative to using the conv and drdy pins. communications packet structure the bq76pl536 -q1 has two primary communication modes via the spi interface. these two modes enable single-byte read / write and multiple data reads. all writes are single-byte; the logical address is shifted one bit left, and the lsb = 1 for writing. all transactions are in the form of packets comprising: byte description #1 6-bit bq76pl536 -q1 slave address + r/w bit 0b0xxx xxxw #2 starting data-register offset #3 number of data bytes to be read (n) (omitted for writes) #4 to 3+n data bytes #4+n crc (omit if io_config[crc_dis] = 1) crc algorithm the cyclic redundancy check (crc) is a crc-8 error-checking byte, calculated on all the message bytes (including addresses). it is identical in structure to the smbus 2.0 packet error check (pec), and is also known as the atm-8 crc. the crc is appended to the message for all spi packets by the device that supplied the data as the last byte in the packet (when io_control[crc] == 1). each bus transaction requires a crc calculation by both the transmitter and receiver within each packet. the crc is calculated in a way that conforms to the polynomial, c(x) = x 8 + x 2 + x 1 + 1 and must be calculated in the order of the bits as received, msb first. the crc calculation includes all bytes in the transmission, including address, command, and data. when reading data from the device, the crc is based on the address + first_register + length + returned_device_data[n]. the stuff-bytes used to clock out the data from the ic are not used as part of the calculation, although if the value 0x00 is used, the 0s have no effect on the crc. crc verification is performed by the receiver when the cs_x line goes false, indicating the end of a packet. if the crc verification fails, the message is ignored (discarded), the crc failure flag is set in the fault_status[crc] register, and the fault line becomes asserted and latched until the error is read and cleared by the host. the crc bit returned in the fault_status[] register reflects the last packet received, not the crc condition of the packet reading the fault_status contents. crc errors should be handled at a high priority by the host controller, before writing to additional registers. data packet usage examples the bq76pl536 -q1 can be enabled via the host to read just the specific voltage data which would require a total of 2 written bytes (chip address and r/w [#1] + first (starting) register offset [#2]) + length [#3] and 13 < null > stuff bytes (12 [n] data bytes + crc). 30 copyright ? 2011, texas instruments incorporated reg address 0 device address 1 reg data crc r/w write packet cs assertion BQ76PL536-Q1 www.ti.com slusab1 C may 2011 the data packet can be periodically expanded to accommodate temperature and gpai readings as well as device status as needed by changing the register_first offset and length values. device addressing each individual device in the series stack requires an address to allow it to be communicated with. each bq76pl536 -q1 has a cs_s and cs_n that are used in assigning addresses. once addresses have been assigned, the normal operation of the cs_n/s lines is asserted (logic high) during communications, and the appropriate bq76pl536 -q1 in the stack responds according to the address transmitted as part of the packet. when the bq76pl536 -q1 is reset, the device_status[ar] (address request) flag is cleared, the address register is set to 0x00, and alert_s is set and passed down the stack. in this state, where address = 0x00, the cs_n signal is forced to a de-asserted state (cs is not passed north when an address = 0). in this manner, after a reset the host is assured that a response at address 0x00 is from the first physical device in the stack. after address assignment of the current device, the host is assured that the next response at address 0x00 is from the next physical device in the stack. once a valid address is assigned to the device, the cs_n signal responds normally, and follows the cs_h or cs_s signal, propagating to the next device in the stack. valid addresses are in the range 0x01 through 0x3e. 0x00 is reserved for device discovery after reset. 0x3f is reserved as a broadcast address for all devices. designer note: broadcast messages are only received by devices with a valid address, and the next higher device. any device with an address of 0x00 blocks messages to devices above it. a broadcast message may not be received by all devices in a stack in situations where some devices do not have a valid address. copyright ? 2011, texas instruments incorporated 31 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com figure 12. address discovery and assignment algorithm 32 copyright ? 2011, texas instruments incorporated send broadcast_reset all devices: address = 0x?? (unknown) expected = # devices in stack note: validated = one more than devices found at this point assign address write dev[0]addr_ctrl = n n < look_for? n < expected? n == expected? dev[n]addr_ctrl[] = n? assign unique address (n) tothis device @address 0x00 validation test: read same device for unique address (n) just assigned validate device was successfully found and addressed this loop finds one device per iteration new (implied: n == look_for here) n y y y n n n success all devices found? start look_for = 0; error() look_for++; n = 0; read dev[n] addr_ctrl[] n++; y this loop resets all addresseddevices, then looks for all previously found+1 devices again. corrects any addressing faults in the stack (implied: n == expected here) BQ76PL536-Q1 www.ti.com slusab1 C may 2011 once the address is written, the address_control[ar] bit is set which is copied to the device_status[ar] and also alert_s if alert_n is also de-asserted. this allows the cs_n pin to follow (asserted) the cs_s pin assertions. the process of addressing can now be repeated as device n has a new address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack. if a device loses its address through a por or it is replaced then this device will be the highest logical device in the stack able to be addressed (0x00) as its cs_n will be disabled and the addressing process is required to be undertaken for this, and higher devices. register architecture i/o register details the bq76pl536 -q1 has 48 addressable i/o registers. these registers provide status, control, and configuration information for the battery protection system. reserved registers return 0x00. unused registers should not be written to; the results are undefined. unused or undefined bits should be written as zeros, and will always read back as zeros. several types of registers are provided, detailed as follows. register types read-only (group 1) these registers contain the results of conversions, or device status information set by internal logic. the contents are re-initialized by a device reset as a result of either por or the reset command. contents of the register are changed by either a conversion command, or when there is an internal state change (i.e., a fault condition is sensed). read / write (group 2) this register group modifies the operations or behavior of the device, or indicates detailed status in the alert_status[] and fault_status[] registers. the contents are re-initialized by a device reset as a result of either por or the reset command. contents of the register are changed either by a conversion command, or when there is an internal state change (i.e., a fault condition is sensed). contents may also be changed by a write from the host cpu to the register. writes may only modify a single register at a time. if crcs are enabled, the write packet is buffered until the crc is checked for correctness. packets with bad crcs are discarded without writing the value to the register, after setting the fault_status[crc] flag. unused or undefined bits in any register should be written as zeros, and will always read back as zeros. figure 13. register group2 architecture copyright ? 2011, texas instruments incorporated 33 register 7 crc_err write 6 5 4 3 2 1 0 internal data bus control, status & data registers fault _status flags crc check logic spi de -serializer BQ76PL536-Q1 slusab1 C may 2011 www.ti.com read / write, initialized from eprom (group3) these registers control the device configuration and functionality. the contents of the registers are initialized from eprom-stored constants as a result of por, reset command, or the reload_shadow command. this feature ensures that the secondary protector portion of the device (cov, cuv, ot) is fully functional after any reset, without host cpu involvement. these registers may only be modified by using a special, sequential-write sequence to guard against accidental changes. the value loaded from eprom at reset (or by command) may be temporarily overridden by using the special write sequence. the temporary value is overwritten to the programmed eprom initialization value by the next reset or command to reload. to write to a these protected registers, first write 0x35 to shdw_control[], immediately followed by the write to the desired register. any intervening write cancels the special sequence. to re-initialize the entire set of group3 registers to the eprom defaults, write the value 0x27 to shdw_control[]. these registers are further protected against corruption by a ninth parity bit that is automatically updated when the register is written using even parity. if the contents of the register ever become corrupted, the bad parity causes the alert_status[parity] bit to become set, alerting the host cpu of the problem. the eprom-stored constants are programmed by writing the values to the register(s), then applying the programming voltage to the ldodx pins, then issuing the eprom_write command to register e_en[]. all group3 registers are programmed simultaneously, and this operation can only be performed once to the one-time-programmable (otp) memory cells. the process is not reversible. figure 14. protected register group3 architecture, simplified view error checking and correcting (ecc) eprom the eprom used to initialize this group is also protected by error-check-and-correct (ecc) logic. the ecc bits provide a highly reliable storage solution in the presence of external disturbances. this feature cannot be disabled by user action. implementation is fully self-contained and automatic and requires no special computations or provisioning by the user. when the group3 contents are permanently written to eprom, an additional array of hidden ecc-otp cells is also automatically programmed. the ecc logic implements a hamming code that automatically corrects all single-bit errors in the eprom array, and senses additional multi-bit errors. if any corrections are made, the device_status[ecc_cor] flag bit is set. if any multi-bit errors are sensed, the alert_status[ecc_err] flag is set. the corrective action or detection is performed anytime the contents of eprom are loaded into the registers C por, reset , or by shadow_load command. note: the ecc_cor and ecc_err bits may glitch during otp-eprom writes; this is normal. if this occurs, reset the tripped bit; it should remain cleared. 34 copyright ? 2011, texas instruments incorporated protected register eprom error check / correct (ecc) logic 7 load program 7 parity ecc_cor ecc_err refresh por refresh-protect key voltage & timing control pgm-protect key write-protect key write load signal evaluatesecc syndrome bits key requires sequenced write to unlock function 6 6 5 5 4 4 3 3 2 2 1 1 0 0 p parity logic check bits internal data bus syndrome checker / generator c n+1... c n c 0 register control & status bits status flags no direct access to this register. 1 bit error 2+ bit errors crc check logic spi de-serializer BQ76PL536-Q1 www.ti.com slusab1 C may 2011 when a double-bit (uncorrectable) error is found, device_status[alert] is set, the alert_s (alert_h for bottom stack device) line is activated, and the alert_status[] register returns the ecc_err and/or i_fault bit = 1(true). the device may return erroneous measurement data, and/or fail to detect cov, cuv, or ot faults in this state. eprom bits are shipped from the factory set to 0, and must be programmed to the 1 state as required. table 3. data and control register descriptions name addr group access (1) reset description device_status 0x00 1 r 0 status register gpai 0x01, 0x02 1 r 0 gpai measurement data vcell1 0x03, 0x04 1 r 0 cell 1 voltage data vcell2 0x05, 0x06 1 r 0 cell 2 voltage data vcell3 0x07, 0x08 1 r 0 cell 3 voltage data vcell4 0x09, 0x0a 1 r 0 cell 4 voltage data vcell5 0x0b, 0x0c 1 r 0 cell 5 voltage data vcell6 0x0d, 0x0e 1 r 0 cell 6 voltage data temperature1 0x0f, 0x10 1 r 0 ts1+ to ts1 C differential voltage data temperature2 0x11, 0x12 1 r 0 ts2+ to ts2 C differential voltage data rsvd 0x13 C 0x1f C C C reserved for future use alert_status 0x20 2 r/w 0x80 indicates source of alert signal fault_status 0x21 2 r/w 0x08 indicates source of fault signal cov_fault 0x22 1 r 0 indicates cell in ov fault state cuv_fault 0x23 1 r 0 indicates cell in uv fault state presult_a 0x24 1 r 0 parity result of group3 protected registers (a) presult_b 0x25 1 r 0 parity result of group3 protected registers (b) rsvd 0x26 C 0x2f C C C reserved for future use adc_control 0x30 2 r/w 0 adc measurement control io_control 0x31 2 r/w 0 i/o pin control cb_ctrl 0x32 2 r/w 0 controls the state of the cell-balancing outputs cbx cb_time 0x33 2 r/w 0 configures the cb control fets maximum on time adc_convert 0x34 2 r/w 0 adc conversion start rsvd 0x35 C 0x39 C C C reserved for future use shdw_ctrl 0x3a 2 r/w 0 controls write access to group3 registers address_control 0x3b 2 r/w 0 address register reset 0x3c 2 w 0 reset control register test_select 0x3d 2 r/w 0 test mode selection register rsvd 0x3e C C C reserved for future use e_en 0x3f 2 r/w 0 eprom programming mode enable function_config 0x40 3 r/w eprom default configuration of device io_config 0x41 3 r/w eprom i/o pin configuration config_cov 0x42 3 r/w eprom overvoltage set point config_covt 0x43 3 r/w eprom overvoltage time-delay filter config_cuv 0x44 3 r/w eprom undervoltage setpoint config_cuvt 0x45 3 r/w eprom undervoltage time-delay filter config_ot 0x46 3 r/w eprom overtemperature set point config_ott 0x47 3 r/w eprom overtemperature time-delay filter user1 0x48 3 r eprom user data register 1, not used by device user2 0x49 3 r eprom user data register 2, not used by device user3 0x4a 3 r eprom user data register 3, not used by device (1) key: r = read; w = write copyright ? 2011, texas instruments incorporated 35 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com table 3. data and control register descriptions (continued) name addr group access (1) reset description user4 0x4b 3 r eprom user data register 4, not used by device rsvd 0x4c C 0xff C C C reserved 36 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 register details device_status register (0x00) 7 6 5 4 3 2 1 0 ar fault alert C ecc_cor uvlo cbt drdy the status register provides information about the current state of the bq76pl536 -q1. [7] this bit is written to indicate that the addr[0] [5] bits have been written to the correct (addr_rqst) address. this bit is a copy of in the address_control[ar] bit. 0 = address has not been assigned 1 = address has been assigned [6] (fault): this bit indicates that this bq76pl536 -q1 has detected a condition causing the fault signal to become asserted. 0 = no fault exists 1 = a fault exists. read fault_status[] to determine the cause. [5] (alert): this bit indicates that this bq76pl536 -q1 has detected a condition causing the alert pin to become asserted. 0 = no fault exists 1 = an alert exists. read alert_status[] to determine the cause. [4] (not implemented) [3] (ecc_cor): this bit indicates a one-bit error has been detected and corrected in the eprom. 0 = no errors are detected in the eprom 1 = a one-bit (single bit) error has been detected and corrected by on-chip logic. [2] (uvlo): this bit indicates the device vbat has fallen below the undervoltage lockout trip point. some device operations are not valid in this condition. 0 = normal operation 1 = uvlo trip point reached, device operation is not ensured. [1] (cbt): this bit indicates the cell balance timer is running. 0 = the cell balance timer is has not started or has expired. 1 = the cell balance timer is running. [0] (drdy): this bit indicates the data is ready to read (no conversions active). 0 = there are conversion(s) running. 1 = there are no conversion(s) running. copyright ? 2011, texas instruments incorporated 37 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com gpai (0x01, 0x02) 15 14 13 12 11 10 9 8 gpai[15] gpai [14] gpai [13] gpai [12] gpai [11] gpai [10] gpai [9] gpai [8] 7 6 5 4 3 2 1 0 gpai [7] gpai [6] gpai [5] gpai [4] gpai [3] gpai [2] gpai [1] gpai [0] the gpai register reports the adc measurement of gpai+/gpai C in units of lsbs. bits 15 C 8 are returned at address 0x01, bits 7 C 0 at address 0x02. vcelln register (0x03 0x0e) 15 14 13 12 11 10 9 8 vcelln[15] vcelln[14] vcelln[13] vcelln[12] vcelln[11] vcelln[10] vcelln[9] vcelln[8] 7 6 5 4 3 2 1 0 vcelln[7] vcelln[6] vcelln[5] vcelln[4] vcelln[3] vcelln[2] vcelln[1] vcelln[0] the vcelln registers report the converted data for cell n, where n = 1 to 6. bits 15 C 8 are returned at odd addresses (e.g. 0x03), bits 7 C 0 at even addresses (e.g. 0x04). temperature1 register (0x0f, 0x10) 15 14 13 12 11 10 9 8 temp1[15] temp1[14] temp1[13] temp1[12] temp1[11] temp1[10] temp1[9] temp1[8] 7 6 5 4 3 2 1 0 temp1[7] temp1[6] temp1[5] temp1[4] temp1[3] temp1[2] temp1[1] temp1[0] the temperature1 register reports the converted data for ts1+ to ts1 C . bits 15 C 8 are returned at odd addresses (e.g., 0x0f), bits 7 C 0 at even addresses (e.g., 0x10). temperature2 register (0x11, 0x12) 15 14 13 12 11 10 9 8 temp2[15] temp2[14] temp2[13] temp2[12] temp2[11] temp2[10] temp2[9] temp2[8] 7 6 5 4 3 2 1 0 temp2[7] temp2[6] temp2[5] temp2[4] temp2[3] temp2[2] temp2[1] temp2[0] the temperature2 register reports the converted data for ts2+ to ts2 C . bits 15 C 8 are returned at odd addresses (e.g., 0x11), bits 7 C 0 at even addresses (e.g., 0x12). alert_status register (0x20) 7 6 5 4 3 2 1 0 ar parity ecc_err force tsd sleep ot2 ot1 the alert_status register provides information about the source of the alert signal. the host must clear each alert flag by writing a 1 to the bit that is set. the exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the ic stack and wiring. [7] ar this bit indicates that the addr[0] [5] bits have been written to a valid address. this bit is an inverted copy of the address_control[ar] bit. it is not cleared until an address has been programmed in address_control and a 1 followed by a 0 (two writes) is written to the bit. 0 = address has been assigned. 1 = address has not been assigned (default at reset). 38 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 [6] (parity): this bit is used to validate the contents of the protected group3 registers. 0 = group3 protected register(s) contents are valid. 1 = group3 protected register(s) contents are invalid. group3 registers should be refreshed from otp or directly written from the host. [5] (ecc_err): this bit is used to validate the otp register blocks. 0 = no double-bit errors (a corrected one-bit error may/may not exist) 1 = an uncorrectable error has been detected in the otp-eprom register bank. otp-eprom register(s) are not valid. [4] (force): this bit asserts the alert signal. it can be used to verify correct operation and connectivity of the alert as a part of system self-test. 0 = deassert alert (default) 1 = assert the alert signal. [3] (tsd): this bit indicates thermal shutdown is active. 0 = thermal shutdown is inactive (default). 1 = die temperature has exceeded t sd . [2] (sleep): this bit indicates sleep mode was activated. this bit is only set when sleep is first activated; no continuous alert or sleep status is indicated after the host resets the bit, even if the io_ctrl[sleep] bit remains true. (see io_ctrl[] register for details.) 0 = normal operation 1 = sleep mode was activated. [1] (ot2): this bit indicates an overtemperature fault has been detected via ts2. 0 = temperature is lower than or equal to the v ot2 (or input disabled by io_control[ts2] = 0). 1 = temperature is higher than v ot2 . [0] (ot1): this bit indicates an overtemperature fault has been detected via ts1. 0 = temperature is lower than or equal to the v ot1 (or input disabled by io_control[ts1] = 0). 1 = temperature is higher than v ot1 . fault_status register (0x21) 7 6 5 4 3 2 1 0 C C i_fault force por crc cuv cov the fault_status register provides information about the source of the fault signal. the host must clear each fault flag by writing a 1 to the bit that is set. the exception is bit 4, which may be written 1 or 0 as needed to implement self-test of the ic stack and wiring. [7] (not implemented) [6] (not implemented) [5] (i_fault): the device has failed an internal register consistency check. measurement data and protection function status may not be accurate and should not be used. 0 = no internal register consistency check fault exists. copyright ? 2011, texas instruments incorporated 39 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com 1 = the internal consistency check has failed self-test. the host should attempt to reset the device, see the reset section. if the fault persists, the failure should be considered uncorrectable. [4] (force): this bit asserts the fault signal. it can be used to verify correct operation and connectivity of the fault line as a part of system self-test. 0 = deassert fault (default) 1 = assert the fault signal. [3] (por): this bit indicates a power-on reset (por) has occurred. 0 = no por has occurred since this bit was last cleared by the host. 1 = a por has occurred. this notifies the host that default values have been loaded to group1 and group2 registers, and otp contents have been copied to group3 registers. [2] (crc): this bit indicates a garbled packet reception by the device. 0 = no errors 1 = a crc error was detected in the last packet received. [1] (cuv): this bit indicates that this bq76pl536 -q1 has detected a cell undervoltage (cuv) condition. examine cuv_fault[] to determine which cell caused the alert. 0 = all cells are above the cuv threshold (default). 1 = one or more cells is below the cuv threshold. [0] (cov): this bit indicates that this bq76pl536 -q1 has detected a cell overvoltage (cov) condition. examine cov_fault[] to determine which cell caused the fault. 0 = all cells are below the cov threshold (default). 1 = one or more cells is above the cov threshold. cov_fault register (0x22) 7 6 5 4 3 2 1 0 C C ov[6] ov[5] ov[4] ov[3] ov[2] ov[1] [0..5] (ov[1]..[6]): these bits indicate which cell caused the device_status[cov] flag to be set. 0 = cell[n] does not have an overvoltage fault (default). 1 = cell[n] does have an overvoltage fault. cuv_fault register (0x23) 7 6 5 4 3 2 1 0 C C uv[6] uv[5] uv[4] uv[3] uv[2] uv[1] b0..5 (uv[1]..[6]): these bits indicate which cell caused the device_status[cuv] flag to be set. 0 = cell[n] does not have an undervoltage fault (default). 1 = cell[n] does have an undervoltage fault. parity_h register (0x24) (presult_a (r/o)) 7 6 5 4 3 2 1 0 ott otv cuvt cuvv covt covv io func 40 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 the presult_a register holds the parity result bits for the first eight group3 protected registers. parity_h register (0x25) (presult_b (r/o)) 7 6 5 4 3 2 1 0 0 0 0 0 user4 user3 user2 user1 the presult_b register holds the parity result bits for the second eight group3 protected registers. adc_control register (0x30) 7 6 5 4 3 2 1 0 C adc_on ts2 ts1 gpai cell_sel[2] cell_sel[1] cell_sel[0] the adc_control register controls some features of the bq76pl536 -q1. [7] not implemented. must be written as 0. [6] (adc_on): this bit forces the adc subsystem on. this has the effect of eliminating internal start-up and settling delays, but increases current consumption. 0 = auto mode. adc subsystem is off until a conversion is requested. the adc is turned on, a wait is applied to allow the reference to stabilize. automatically returns to off state at end of requested conversion. note that there is a start-up delay associated with turning the adc to the on state in this mode. 1 = adc subsystem is on, regardless of conversion state. power consumption is increased. [5..4] (ts[1]..[0]): these two bits select whether any of the temperature sensor inputs are to be measured on the next conversion sequence start. ts[1] ts[0] measure t 0 0 none (default) 0 1 ts1 1 0 ts2 1 1 both [3] (gpai): this bit enables and disables the gpai input to be measured on the next conversion-sequence start. 0 = gpai is not selected for measurement. 1 = gpai is selected for measurement. [2 C 0] (cell_sel): these three bits select the series cells for voltage measurement translation on the next conversion sequence start. cell_sel[2] cell_sel[1] cell_sel[0] selected cell 0 0 0 cell 1 only 0 0 1 cells 1-2 0 1 0 cells 1-2-3 0 1 1 cells 1-2-3-4 1 0 0 cells 1-2-3-4-5 1 0 1 cells 1-2-3-4-5-6 other cell 1 only copyright ? 2011, texas instruments incorporated 41 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com io_control register (0x31) 7 6 5 4 3 2 1 0 aux gipi_out gpio_in 0 0 sleep ts2 ts1 the io_control register controls some features of the bq76pl536 -q1 external i/o pins. [7] (aux): controls the state of the aux output pin, which is internally connected to reg50. 0 = open 1 = connected to reg50 [6] (gpio_out): controls the state of the open-drain gpio output pin; the pin should be programmed to 1 to use the gpio pin as an input. 0 = output low 1 = open-drain [5] (gpio_in): represents the input state of gpio pin when used as an input 0 = gpio input is low. 1 = gpio input is high. [4] not implemented. must be written as 0. [3] not implemented. must be written as 0. [2] (sleep): places the device in a low-quiescent-current state. all cuv, cov, and ot comparators are disabled. a 1-ms delay to stabilize the reference voltage is required to exit sleep mode and return to active cov, cuv monitoring. 0 = active mode 1 = sleep mode [1..0] (tsx) controls the connection of the ts1(2) inputs to the adc vss connection point. when set, the tsx( C ) input is connected to vss. these bits should be set to 0 to reduce the current draw of the system. 0 = not connected 1 = connected cb_ctrl register (0x32) 7 6 5 4 3 2 1 0 C C cbal[6] cbal[5] cbal[4] cbal[3] cbal[2] cbal[1] the cb_ctrl register determines the internal cell balance output state. cb_ctrl b(n = 5 to 0) (cbal(n + 1)): this bit determines if the cb(n) output is high or low. 0 = cb[n] output is low (default). 1 = cb[n] output is high (active). 42 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 cb_time register (0x33) 7 6 5 4 3 2 1 0 cbt[7] C cbt[5] cbt[4] cbt[3] cbt[2] cbt[1] cbt[0] the cb_time register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63 minutes. when set to 0, no balancing can occur C balancing is effectively disabled. [7] controls minutes/seconds counting resolution. 0 = seconds (default) 1 = minutes [5..0] sets the time duration as scaled by cbt.7 adc_convert register (0x34) 7 6 5 4 3 2 1 0 C C C C C C C conv the convert_ctrl register is used to start conversions. [0] (conv): this bit starts a conversion, using the settings programmed into the adc_control[] register. it provides a programmatic method of initiating conversions. 0 = no conversion (default) 1 = initiate conversion. this bit is automatically reset after conversion begins, and always returns 0 on read. shdw_ctrl register (0x3a) 7 6 5 4 3 2 1 0 shdw[7] shdw[6] shdw[5] shdw[4] shdw[3] shdw[2] shdw[1] shdw[0] the shdw_ctrl register controls writing to group3 protected registers. default at reset = 0x00. the value 0x35 must be written to this register to allow writing to group3 protected registers in the range 0x40 C 0x4f. the register always returns 0x00 on read. the register is reset to 0x00 after any successful write, including a write to non-group3 registers. a read operation does not reset this register. writing the value 0x27 results in all group3 protected registers being refreshed from otp programmed values. the register is reset to 0x00 after the refresh is complete. copyright ? 2011, texas instruments incorporated 43 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com address_control register (0x3b) 7 6 5 4 3 2 1 0 ar 0 addr[5] addr[4] addr[3] addr[2] addr[1] addr[0] the address_control register allows the host to assign an address to the bq76pl536 -q1 for communication. the default for this register is 0x00 at reset. [7] (addr_rqst): this bit is written to indicate that the addr[0] [5] bits have been written to the correct address. this bit is reflected in the device_status[ar] bit 0 = address has not been assigned (default at reset). 1 = address has been assigned. [5..0] (addr): these bits set the device address for spi communication. this provides to a range of addresses from 0x00 to 0x3f. address 0x3f is reserved for broadcast messages to all connected and addressed 76pl536 devices. the default for these 6 bits is 0x00 at reset. reset register (0x3c) 7 6 5 4 3 2 1 0 rst[7] rst[6] rst[5] rst[4] rst[3] rst[2] rst[1] rst[0] the reset register allows the host to reset the bq76pl536 -q1 directly. writing 0xa5 causes the device to reset. other values are ignored. test_select register (0x3d) 7 6 5 4 3 2 1 0 tsel[7] tsel[6] tsel[5] tsel[4] tsel[3] tsel[2] tsel[1] tsel[0] the test_select places the spi port in a special mode useful for debug. tsel (b7 C b0) is used to place the spi_h interface pins in a mode to support test/debug of a string of bq76pl536 -q1 devices. 0 = normal operating mode. when the sequence 0xa4, 0x25 ("jr") is written on subsequent write cycles, the device enters a special test mode useful for stack debugging. writes to other registers between the required sequence bytes results in the partial sequence being voided; the entire sequence must be written again. por, reset, or writing a 0x00 to this register location exits this mode. in this state, spi pin sclk and sdi become outputs and are enabled, and reflect the state of the sclk_s, sdi_s pins of the device. sdo remains an output. this allows observation of bus traffic mid-string. the lowest device in the string should not be set to operate in this mode. the user is cautioned to condition the connection to a mid- or top-string device with suitable isolation circuitry to prevent injury or damage to connected devices. programming the most-negative device on the stack in this mode prevents further communications with the stack until por, and may result in device destruction; this condition should be avoided. e_en register (0x3f) 7 6 5 4 3 2 1 0 e_en[7] e_en [6] e_en [5] e_en [4] e_en [3] e_en [2] e_en [1] e_en [0] the e_en register controls the access to the programming of the integrated otp eprom. this register should be written the value 0x91 to permit writing the user block of eprom. values other than 0x00 and 0x91 are reserved and may result in undefined operation. the next read or write of any type to the device resets (closes) the write window. if a group3 protected write occurs, the window is closed after the write. 44 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 function_config register (0x40) 7 6 5 4 3 2 1 0 adct[1] adct[0] gpai_ref gpai_src cn[1] cn[0] C 0 the function_config sets the default configuration for special features of the device. [7..6] (adct[0,1]): these bits set the conversion timing of the adc measurement. adct[1] adct[0] ~conversion time ( s) 0 0 3 0 1 6 (recommended) 1 0 12 1 1 24 [5] (gpai_ref): this bit sets the reference for the gpai adc measurement. 0 = internal adc bandgap reference 1 = v reg50 (ratiometric) [4] (gpai_src): this bit controls multiplexing of the gpai register and determines whether the adc mux is connected to the external gpai inputs, or internally to the bat1 pin. the register results are automatically scaled to match the input. 0 = external gpai inputs are converted to result in gpai register 0x01 C 02. 1 = bat pin to vss voltage is measured and reported in the gpai register. [3..2] (cn[1..0]): these two bits configure the number of series cells used. if fewer than 6 cells are configured, the corresponding ov/uv faults are ignored. for example, if the cn[x] bits are set to 10b (2), then the ov/uv comparators are ignored for cells 5 and 6. cn[1] cn[0] series cells 0 0 6 (default) 0 1 5 1 0 4 1 1 3 io_config register (0x41) 7 6 5 4 3 2 1 0 C C C C C C C crc_dis the io_config sets the default configuration for miscellaneous i/o features of the device. [0] (crc_dis): this bit enables and disables the automatic generation of the crc for the spi communication packet. the packet size is determined by the host as part of the read request protocol. the crc is checked at the deassertion of the cs pin. ti recommends that this bit be changed using the broadcast address (0x3f) so that all devices in a battery stack use the same protocol. 0 = a crc is expected, and generated as the last byte of the packet. 1 = a crc is not used in communications. copyright ? 2011, texas instruments incorporated 45 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com config_cov register (0x42) 7 6 5 4 3 2 1 0 disable C cov[5] cov[4] cov[3] cov[2] cov[1] cov[0] the config_cov register determines cell overvoltage threshold voltage. [7] (disable): disables the overvoltage function when set 0 = overvoltage function enabled 1 = overvoltage function disabled [5..0] (cov[5] [0]): configuration bits with corresponding voltage threshold 0x00 = 2 v; each binary increment adds 50 mv until 0x3c = 5 v. config_covt register (0x43) 7 6 5 4 3 2 1 0 s/ms C C covd[4] covd[3] covd[2] covd[1] covd[0] the config_covt register determines cell overvoltage detection delay time. [7] ( s/ms): determines the units of the delay time, microseconds or milliseconds 0 = microseconds 1 = milliseconds [4..0] covd: 0x01 = 100; each binary increment adds 100 until 0x1f = 3100 note: when this register is programmed to 0x00, the delay becomes 0s and the cov state is not latched in the cov_fault[] register. in this operating mode, the overvoltage state for a cell is virtually instantaneous in the cov_fault[] register. this mode may cause system firmware to miss a dangerous cell overvoltage condition. config_uv register (0x44) 7 6 5 4 3 2 1 0 disable C C cuv[4] cuv[3] cuv[2] cuv[1] cuv[0] the cuv register determines cell under voltage threshold voltage. [7] (disable): disables the undervoltage function when set 0 = undervoltage function enabled 1 = undervoltage function disabled [5..0] (cuv[4] [0]): configuration bits with corresponding voltage threshold 0x00 = 0.7 v; each binary increment adds 100 mv until 0x1a = 3.3 v. 46 copyright ? 2011, texas instruments incorporated BQ76PL536-Q1 www.ti.com slusab1 C may 2011 config_cuvt register (0x45) 7 6 5 4 3 2 1 0 s/ms C C cuvd[4] cuvd[3] cuvd[2] cuvd[1] cuvd[0] the config_cuvt register determines cell overvoltage detection delay time. [7] ( s/ms): determines the units of the delay time, microseconds or milliseconds 0 = microseconds 1 = milliseconds [4..0] cuvd: 0x01 = 100; each binary increment adds 100 until 0x1f = 3100. note: when this register is programmed to 0x00, the delay becomes 0s and the cuv state is not latched in the cuv_fault[] register. in this operating mode, the overvoltage state for a cell is virtually instantaneous in the cuv_fault[] register. this mode may cause system firmware to miss a dangerous cell undervoltage condition. config_ot register (0x46) 7 6 5 4 3 2 1 0 ot2[3] ot2[2] ot2[1] ot2[0] ot1[3] ot1[2] ot1[1] ot1[0] the config_ot register holds the configuration of the overtemperature thresholds for the two ts inputs. for each respective nibble (ot1 or ot2), the value 0x0 disables this function. other settings program a trip threshold. see the ratiometric sensing section for details of setting this register. values above 0x0b are illegal and should not be used. config_ott register (0x47) 7 6 5 4 3 2 1 0 cotd[7] cotd[6] cotd[5] cotd[4] cotd[3] cotd[2] cotd[1] cotd[0] the config_ott register determines cell overtemperature detection delay time. 0x01 = 10 ms; each binary increment adds 10 ms until 0xff = 2.55 seconds. note: when this register is programmed to 0x00, the delay becomes 0s and the ot state is not latched in the alert_status[] register. in this operating mode, the overtemperature state for a tsn input is virtually instantaneous in the register. this mode may cause system firmware to miss a dangerous overtemperature condition. userx register (0x48 C 0x4b) (user1 C 4) 7 6 5 4 3 2 1 0 user[7] user[6] user[5] user[4] user[3] user[2] user[1] user[0] the four user registers can be used to store user data. the part does not use these registers for any internal function. they are provided as convenient storage for user s/n, date of manufacture, etc. copyright ? 2011, texas instruments incorporated 47 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com programming the eprom configuration registers the bq76pl536 -q1 has a block of otp-eprom that is used for configuring the operation of the bq76pl536 -q1. programming of the eprom should take place during pack/system manufacturing. a 7-v (v pp ) pulse is required on the prog pin. the part uses an internal window comparator to check the voltage, and times the internal pulse delivered to the eprom array. the user first writes the desired values to all of the equivalent group3 protected register addresses. the desired data is written to the appropriate address by first applying 7 v to the ldod1(2) pins. programming then performed by writing to the ee_en register (address 0x3f) with data 0x91. after a time period > 1500 s, the 7 v is removed. nominally, the voltage pulse should be applied for approximately 2 C 3 ms. applying the voltage for an extended period of time may lead to device damage. the write is self-timed internally after receipt of the command. the following flow chart illustrates the procedure for programming. figure 15. eprom programming 48 copyright ? 2011, texas instruments incorporated enable group3 write: write: 0x35 to shdw_ctrl (0x3a) host enables write to user block write: 0x91 to e_en @0x3f apply 7 v to ldod1(2) pin host writes data to registers in user block 0x40C0x47 write data to registers write: 0xnn to 0x4x addr++ addr > 0x4b? no yes verify data in 0x40C0x47 copy eprom back to registers write 0x27 to shdw_ctrl (0x3a) read register block 0x40C0x4b contents match programmed value? yes no verify ecc bits read device_status [ecc_cor] read alert_status [parity] read alert_status [parity] all == 0? yes no success fail programming complete nominal time ~ 2 ms to 3 ms remove 7 v from ldod1(2) pins BQ76PL536-Q1 www.ti.com slusab1 C may 2011 reference schematic figure 16. schematic (page 1 of 4) copyright ? 2011, texas instruments incorporated 49 cell 12 + cell 11 + cell 10 + cell 9 + cell 8 + cell 7 + cell 7 - cell 18 + cell 17 + cell 16 + cell 15 + cell 14 + cell 13 + cell 13 - the ground (vss) reference per circuit block is unique. do not connect ground references from different ic's. the most negative connection per block "cell0" is theground (vss) reference for each ic. only the ground reference cell0 of circuit 1 is safe toconnect non-isolated test equipment grounds. individual ground planes are necessary for proper noise rejection and stability of these circuits ground plane of circuit 2 ground plane of circuit 3 extend the ground plane under the south comm lines to just below the north comm pins of the chip below locate r142, r175, r192, r193 locate r143, r144, r168, r176 close to the most north ic close to the most south ic close to the most north ic locate r195, r196, r197, r199 caution high voltage notes: e 12 3 4 5 6 7 p2 39502-1007_7-pos 12 3 4 5 6 7 p3 39502-1007_7-pos cell0 cell1 cell2 cell3 cell4 cell5 cell6 conv_ndrdy_n alert_n fault_n sclk_n sdo_n sdi_n cs_n 2-conv_n 2-drdy_n 2-alert_n 2-fault_n 2-sclk_n 2-sdo_n 2-sdi_n 2-cs_n 2-cell1 2-cell2 2-cell3 2-cell4 2-cell5 2-cell6 2-cell0 2-vbat bq76pl536_circuit2 sheet-3 vbat cell0 cell1 cell2 cell3 cell4 cell5 cell6 conv_ndrdy_n alert_n fault_n sclk_n sdo_n sdi_n cs_n conv_sdrdy_s alert_s fault_s sclk_s sdo_s sdi_s cs_s 3-vbat 3-vbat 3-vbat 3-vbat 3-vbat 3-vbat 3-vbat 3-vbat 3-cell1 3-cell2 3-cell3 3-cell4 3-cell5 3-cell6 3-cell0 3-conv_s3-drdy_s 3-alert_s 3-fault_s 3-sclk_s 3-sdo_s 3-sdi_s 3-cs_s 3-vbat bq76pl536_circuit3 sheet-4 tp3 tp4 tp5 tp6 r143 res0603 1k r142 res0603 1k r144 res0603 1k r145 res0603 1k r146 res0603 1k r147 res0603 1k r148 res0603 1k r149 res0603 1k c84 .001uf 50v cap0603 c85 .0033uf 50v cap0603 3-vss 2-vss 3-vss 2-vss cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + cell 1 - cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + cell 1 - fault alert drdy conv gnd vsig mosics sclk miso ground plane of circuit 1 ground plane of circuit 2 close to the most south ic locate r194, r198, r200, r201 caution high voltage 12 3 4 5 6 7 p1 39502-1007_7-pos conv_ndrdy_n alert_n fault_n sclk_n sd0_n sdi_n cs_n fault alert drdyconv spi-misospi-mosi spi-sclk spi-ss cs_s sdi_s sd0_s sclk_s fault_s alert_s drdy_s conv_s cell0 cell1 cell2 cell3 cell4 cell5 cell6 1-conv_n 1-drdy_n 1-alert_n 1-fault_n 1-sclk_n 1-sdo_n 1-sdi_n 1-cs_n 1-cell1 1-cell2 1-cell3 1-cell4 1-cell5 1-cell6 1-cell0 1-cell01-cell0 1-cell0 1-cell0 1-cell0 1-cell01-cell0 1-cell0 1-fault 1-alert 1-drdy/tx 1-conv/rx 1-spi-miso1-spi-mosi 1-spi-sclk 1-spi-ss 1-vbat bq76pl536_circuit1 sheet-2 conv_sdrdr_s alert_s fault_s sclk_s sdo_s sdi_s cs_s 2-conv_s2-drdy_s 2-alert_s 2-fault_s 2-sclk_s 2-sdo_s 2-sdi_s 2-cs_s tp1 tp2 12 3 4 5 6 7 8 9 10 p4 mta100-header-10pin r81 res0603 1k r82 res0603 1k r83 res0603 1k r84 res0603 1k r85 res0603 1k r86 res0603 1k r91 res0603 1k r92 res0603 1k c51 .001uf 50v cap0603 c52 .0033uf 50v cap0603 r12 res0603 100 r13 res0603 100 r14 res0603 100 r15 res0603 100 2-vss 1-vss 1-vss 2-vss 1-vss 1-vss s001 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com figure 17. schematic (page 2 of 4) 50 copyright ? 2011, texas instruments incorporated t1 t2 cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + cell 1 - "bottom" part connectsall _s pins to 1-vss. ** t1 t2 cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + ** ** ** ** ** ** ** ** ** ** ** thermistor ntc 10k ohm 1% 0603 panasonic part number # ert-j1vg103fa ** - locate these components very close to bq76pl536 ic. caution high voltage caution high voltage ground plane of circuit 2 ground plane of circuit 1 * - typical value shown. actual value depends on number of ic's in stack, wiring, etc. consult applications guide for recommended values. * * * * c26 cap0805 2.2uf 10v c24 cap0805 2.2uf 10v c39cap0805 2.2uf 10v c23 cap1206 10uf 10v q2 sot-23 fdn359an r9 res2512 47 r18 res0603 1.0k 1% 1 vc6 2 cb6 3 vc5 4 cb5 5 vc4 6 cb4 7 vc3 8 cb3 9 vc2 10 cb2 11 vc1 12 cb1 13 vc0 14 vss1 15 agnd 16 vref 17 ldoa 18 ldod1 19 ts1- 20 ts1+ 21 conv_s 22 drdy_s 23 alert_s 24 fault_s 25 vss2 26 sclk_s 27 sdo_s 28 sdi_s 29 cs_s 30 nc1 31 aux 32 reg50 33 vss3 34 vss4 35 vss5 36 conv_h 37 drdy_h 38 alert_h 39 fault_h 40 sclk_h 41 sdo_h 42 sdi_h 43 cs_h 44 hsel 45 gpio 46 ldod2 47 gpai- 48 gpai+ 49 vss6 50 test 51 nc2 52 cs_n 53 sdi_n 54 sdo_n 55 sclk_n 56 fault_n 57 alert_n 58 drdy_n 59 conv_n 60 ts2- 61 ts2+ 62 nc3 63 bat1 64 bat2 65 tab u1bq76pl536 q4 sot-23 fdn359an r24 res2512 47 r28 res0603 1.0k 1% q6 sot-23 fdn359an r38 res2512 47 r40 res0603 1.0k 1% q7 sot-23 fdn359an r49 res2512 47 r57 res0603 1.0k 1% q8 sot-23 fdn359an r69 res2512 47 r75 res0603 1.0k 1% q9 sot-23 fdn359an r79 res2512 47 r80 res0603 1.0k 1% z11 5.1 vdc 500mw sod-123 z95.1 vdc 500mw sod-123 z75.1 vdc 500mw sod-123 z55.1 vdc 500mw sod-123 z35.1 vdc 500mw sod-123 z15.1 vdc 500mw sod-123 c43cap0603 0.1uf 50v r76 res0603 1m 1% r61 res0603 1m 1% r44 res0603 1m 1% r35 res0603 1m 1% r21 res0603 1m 1% r7 res0603 1m 1% r50 0r0 res0603 r58 0r0 res0603 c34 cap0603 0.1uf 50v c48cap0603 0.1uf 50v c42 cap0603 0.1uf 50v c37cap0603 0.1uf 50v c27 cap0603 0.1uf 50v c19cap0603 0.1uf 50v c9 cap0603 0.1uf 50v r33 1.82k 1% res0603 r63 1.82k 1% res0603 r711.47k 1% res0603 r27 1.47k 1% res0603 c21cap0603 0.047uf 16v c46cap0603 0.047uf 16v r123 ntc0603 b=3435k 10k 1% r124 ntc0603 b=3435k 10k 1% q5 2n7002lt1 sot-23 r30 res0603 100 r25 res0603 2.7k d1 ltw-c192tl2 white led r29 100k res0603 tp-vprog1 r8 res0603 1.0k 1% r22 res0603 1.0k 1% r32 res0603 1.0k 1% r45 res0603 1.0k 1% r62 res0603 1.0k 1% r77 res0603 1.0k 1% c25cap0603 0.1uf 50v z12 5.1vdc sod-323 z10 5.1vdc sod-323 z8 5.1vdc sod-323 z6 5.1vdc sod-323 z4 5.1vdc sod-323 z2 5.1vdc sod-323 c30 cap0603 0.1uf 50v c32 cap0603 0.1uf 50v c33 cap0603 0.1uf 50v c38 cap0603 0.1uf 50v c40 cap0603 0.1uf 50v c41 cap0603 0.1uf 50v tp-vss1 c113 cap0603 33pf 50v c105cap0603 33pf 50v c47 cap0603 33pf 50v c108 cap0603 33pf 50v c4 cap0603 dnp c6 cap0603 dnp c7 cap0603 dnp 1-cell1 [1] 1-cell2 [1] 1-cell3 [1] 1-cell4 [1] 1-cell5 [1] 1-cell6 [1] 1-vss [1,2] 1-conv_s1-drdy_s 1-alert_s 1-fault_s 1-sclk_s1-sdo_s 1-sdi_s 1-cs_s 1-fault [1] 1-alert [1] 1-drdy/tx [1] 1-conv/rx [1] 1-spi-miso [1] 1-spi-mosi [1] 1-spi-sclk [1] 1-spi-ss [1] 1-vss 1-vss 1-vss 1-vss 1-vss 1-ldoa 1-ldod 1-vss 1-vss 1-vss 1-conv_n [1] 1-drdy_n [1] 1-alert_n [1] 1-fault_n [1] 1-sclk_n [1] 1-sdo_n [1] 1-sdi_n [1] 1-cs_n [1] 1-vbat [1] 1-vss 1-vss 1-vss 1-vss 1-vss 1-vss 1-vss s002 BQ76PL536-Q1 www.ti.com slusab1 C may 2011 figure 18. schematic (page 3 of 4) copyright ? 2011, texas instruments incorporated 51 t1 t2 cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + cell 1 - t1 t2 cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + cell 1 - ** ** ** ** ** ** ** ** ** ** ** ** thermistor ntc 10k ohm 1% 0603 panasonic part number # ert-j1vg103fa ** - locate these components very close to bq76pl536 ic. caution high voltage caution high voltage ground plane of circuit 3 ground plane of circuit 2 extend the ground plane under the south comm lines to just below the north comm pins of the chip below ground plane of circuit 2 * * * * * * * * * - typical value shown. actual value depends on number of ic's in stack, wiring, etc. consult applications guide for recommended values. c63 cap0805 2.2uf 10v c61 cap0805 2.2uf 10v c71cap0805 2.2uf 10v c60 cap1206 10uf 10v q10 sot-23 fdn359an r98 res2512 47 r99 res0603 1.0k 1% 1 vc6 2 cb6 3 vc5 4 cb5 5 vc4 6 cb4 7 vc3 8 cb3 9 vc2 10 cb2 11 vc1 12 cb1 13 vc0 14 vss1 15 agnd 16 vref 17 ldoa 18 ldod1 19 ts1- 20 ts1+ 21 conv_s 22 drdy_s 23 alert_s 24 fault_s 25 vss2 26 sclk_s 27 sdo_s 28 sdi_s 29 cs_s 30 nc1 31 aux 32 reg50 33 vss3 34 vss4 35 vss5 36 conv_h 37 drdy_h 38 alert_h 39 fault_h 40 sclk_h 41 sdo_h 42 sdi_h 43 cs_h 44 hsel 45 gpio 46 ldod2 47 gpai- 48 gpai+ 49 vss6 50 test 51 nc2 52 cs_n 53 sdi_n 54 sdo_n 55 sclk_n 56 fault_n 57 alert_n 58 drdy_n 59 conv_n 60 ts2- 61 ts2+ 62 nc3 63 bat1 64 bat2 65 tab u2bq76pl536 q11 sot-23 fdn359an r104 res2512 47 r109 res0603 1.0k 1% q13 sot-23 fdn359an r114 res2512 47 r117 res0603 1.0k 1% q14 sot-23 fdn359an r121 res2512 47 r128 res0603 1.0k 1% q15 sot-23 fdn359an r132 res2512 47 r135 res0603 1.0k 1% q16 sot-23 fdn359an r139 res2512 47 r140 res0603 1.0k 1% z245.1 vdc 500mw sod-123 z225.1 vdc 500mw sod-123 z205.1 vdc 500mw sod-123 z185.1 vdc 500mw sod-123 z165.1 vdc 500mw sod-123 z145.1 vdc 500mw sod-123 c75cap0603 0.1uf 50v r136 res0603 1m 1% r129 res0603 1m 1% r119 res0603 1m 1% r110 res0603 1m 1% r100 res0603 1m 1% r94 res0603 1m 1% c69cap0603 0.1uf 50v c81cap0603 0.1uf 50v c76 cap0603 0.1uf 50v c72cap0603 0.1uf 50v c65 cap0603 0.1uf 50v c58cap0603 0.1uf 50v c54 cap0603 0.1uf 50v r115 100k res0603 r157 ntc0603 b=3435k 10k 1% r158 ntc0603 b=3435k 10k 1% c78cap0603 0.047uf 16v c59cap0603 0.047uf 16v r1341.47k 1% res0603 r103 1.47k 1% res0603 r131 1.82k 1% res0603 r107 1.82k 1% res0603 q12 2n7002lt1 sot-23 r106 res0603 100 r102 res0603 2.7k d4 ltw-c192tl2 white led r105100k res0603 tp-vprog2 r95 res0603 1.0k 1% r101 res0603 1.0k 1% r111 res0603 1.0k 1% r120 res0603 1.0k 1% r130 res0603 1.0k 1% r137 res0603 1.0k 1% c62cap0603 0.1uf 50v z25 5.1vdc sod-323 z23 5.1vdc sod-323 z21 5.1vdc sod-323 z19 5.1vdc sod-323 z17 5.1vdc sod-323 z15 5.1vdc sod-323 c66 cap0603 0.1uf 50v c67 cap0603 0.1uf 50v c68 cap0603 0.1uf 50v c70 cap0603 0.1uf 50v c73 cap0603 0.1uf 50v c74 cap0603 0.1uf 50v tp-vss2 c82 cap0603 33pf 50v c83cap0603 33pf 50v c80 cap0603 33pf 50v c79 cap0603 33pf 50v c57 cap0603 33pf 50v c55 cap0603 33pf 50v c53 cap0603 1nf 50v c56 cap0603 1nf 50v r1 0r0 res0603 r3 0r0 res0603 c8 cap0603 dnp c10 cap0603 dnp c11 cap0603 dnp 2-cell1 [1] 2-cell2 [1] 2-cell3 [1] 2-cell4 [1] 2-cell5 [1] 2-cell6 [1] 2-vss [1,3] 2-vss 2-vss 2-vss 2-vss 2-vss 2-vss 2-ldoa 2-vss 2-ldod [3] 2-vss 2-conv_n [1] 2-drdy_n [1] 2-alert_n[1] 2-fault_n [1] 2-sclk_n [1] 2-sdo_n [1] 2-sdi_n [1] 2-cs_n [1] 2-conv_s [1] 2-drdy_s [1] 2-alert_s [1] 2-fault_s [1] 2-sclk_s [1] 2-sdo_s [1] 2-sdi_s [1] 2-cs_s [1] 2-vss 2-vss 2-vss 2-vss 2-vbat [1] 2-vss 2-ldod[3] 2-vss 2-vss 2-vss 2-vss 2-vss 2-vss s003 BQ76PL536-Q1 slusab1 C may 2011 www.ti.com figure 19. schematic (page 4 of 4) full-size reference schematics are available from ti on request. 52 copyright ? 2011, texas instruments incorporated t1 t2 cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + cell 1 - "top" part connects t1 t2 cell 6 + cell 5 + cell 4 + cell 3 + cell 2 + cell 1 + cell 1 - all _n pins to cell6 of u3 ** ** ** ** ** ** ** ** ** ** ** ** thermistor ntc 10k ohm 1% 0603 panasonic part number # ert-j1vg103fa ** - locate these components very close to bq76pl536 ic. caution high voltage caution high voltage extend the ground plane under the south comm lines to just below the north comm pins of the chip below ground plane of circuit 3 * - typical value shown. actual value depends on number of ic's in stack, wiring, etc. consult applications guide for recommended values. * * * * c92cap0805 2.2uf 10v c90 cap0805 2.2uf 10v c100cap0805 2.2uf 10v c89 cap1206 10uf 10v q17 sot-23 fdn359an r155 res2512 47 r160 res0603 1.0k 1% 1 vc6 2 cb6 3 vc5 4 cb5 5 vc4 6 cb4 7 vc3 8 cb3 9 vc2 10 cb2 11 vc1 12 cb1 13 vc0 14 vss1 15 agnd 16 vref 17 ldoa 18 ldod1 19 ts1- 20 ts1+ 21 conv_s 22 drdy_s 23 alert_s 24 fault_s 25 vss2 26 sclk_s 27 sdo_s 28 sdi_s 29 cs_s 30 nc1 31 aux 32 reg50 33 vss3 34 vss4 35 vss5 36 conv_h 37 drdy_h 38 alert_h 39 fault_h 40 sclk_h 41 sdo_h 42 sdi_h 43 cs_h 44 hsel 45 gpio 46 ldod2 47 gpai- 48 gpai+ 49 vss6 50 test 51 nc2 52 cs_n 53 sdi_n 54 sdo_n 55 sclk_n 56 fault_n 57 alert_n 58 drdy_n 59 conv_n 60 ts2- 61 ts2+ 62 nc3 63 bat1 64 bat2 65 tab u3bq76pl536 q18 sot-23 fdn359an r167 res2512 47 r170 res0603 1.0k 1% q20 sot-23 fdn359an r177 res2512 47 r179 res0603 1.0k 1% q21 sot-23 fdn359an r183 res2512 47 r185 res0603 1.0k 1% q22 sot-23 fdn359an r193 res2512 47 r196 res0603 1.0k 1% q23 sot-23 fdn359an r199 res2512 47 r208 res0603 1.0k 1% z375.1 vdc 500mw sod-123 z355.1 vdc 500mw sod-123 z335.1 vdc 500mw sod-123 z315.1 vdc 500mw sod-123 z295.1 vdc 500mw sod-123 z275.1 vdc 500mw sod-123 c104cap0603 0.1uf 50v r197 res0603 1m 1% r186 res0603 1m 1% r180 res0603 1m 1% r173 res0603 1m 1% r162 res0603 1m 1% r152 res0603 1m 1% c98cap0603 0.1uf 50v c114 cap0603 0.1uf 50v c109 cap0603 0.1uf 50v c101cap0603 0.1uf 50v c94 cap0603 0.1uf 50v c87cap0603 0.1uf 50v c86 cap0603 0.1uf 50v r178 100k res0603 r191 ntc0603 b=3435k 10k 1% r192 ntc0603 b=3435k 10k 1% r1941.47k 1% res0603 r165 1.47k 1% res0603 r188 1.82k 1% res0603 r171 1.82k 1% res0603 c88cap0603 0.047uf 16v c111 cap0603 0.047uf 16v q19 2n7002lt1 sot-23 r169 res0603 100 r164 res0603 2.7k d5 ltw-c192tl2 white led r168100k res0603 tp-vprog3 r198 res0603 1.0k 1% r187 res0603 1.0k 1% r181 res0603 1.0k 1% r174 res0603 1.0k 1% r163 res0603 1.0k 1% r153 res0603 1.0k 1% c91 cap0603 0.1uf 50v z39 5.1vdc sod-323 z36 5.1vdc sod-323 z34 5.1vdc sod-323 z32 5.1vdc sod-323 z30 5.1vdc sod-323 z28 5.1vdc sod-323 c103 cap0603 0.1uf 50v c102 cap0603 0.1uf 50v c99 cap0603 0.1uf 50v c97 cap0603 0.1uf 50v c96 cap0603 0.1uf 50v c95 cap0603 0.1uf 50v tp-vss3 c5 cap0603 33pf 50v c1 cap0603 33pf 50v c3 cap0603 1nf 50v c2 cap0603 1nf 50v r4 0r0 res0603 r5 0r0 res0603 c12 cap0603 dnp c13 cap0603 dnp c14 cap0603 dnp 3-conv_n3-drdy_n 3-alert_n 3-fault_n 3-sclk_n 3-sdo_n 3-sdi_n 3-cs_n 3-cell1 [1] 3-cell2 [1] 3-cell3 [1] 3-cell4 [1] 3-cell5 [1] 3-cell6 [1] 3-vss [1,4] 3-vss 3-vss 3-vss 3-vss 3-vss 3-vss 3-ldoa 3-vss 3-ldod [4] 3-vbat [1] 3-vss 3-conv_s [1] 3-drdy_s [1] 3-alert_s [1] 3-fault_s [1] 3-sclk_s [1] 3-sdo_s [1] 3-sdi_s [1] 3-cs_s [1] 3-vss 3-vss 3-vss 3-vss 3-reg50 3-vss 3-ldod [4] 3-vss 3-vss 3-vss 3-vss 3-vss 3-vss s004 package option addendum www.ti.com 13-jul-2011 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) bq76pl536tpaprq1 active htqfp pap 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr bq76pl536tpaptq1 active htqfp pap 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of BQ76PL536-Q1 : ? catalog: bq76pl536 note: qualified version definitions: package option addendum www.ti.com 13-jul-2011 addendum-page 2 ? catalog - ti's standard catalog product tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant bq76pl536tpaprq1 htqfp pap 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 q2 bq76pl536tpaptq1 htqfp pap 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.0 q2 package materials information www.ti.com 15-jul-2011 pack materials-page 1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) bq76pl536tpaprq1 htqfp pap 64 1000 346.0 346.0 41.0 bq76pl536tpaptq1 htqfp pap 64 250 346.0 346.0 41.0 package materials information www.ti.com 15-jul-2011 pack materials-page 2 important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti ? s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or " enhanced plastic. " only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer ' s risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications audio www.ti.com/audio communications and telecom www.ti.com/communications amplifiers amplifier.ti.com computers and peripherals www.ti.com/computers data converters dataconverter.ti.com consumer electronics www.ti.com/consumer-apps dlp ? products www.dlp.com energy and lighting www.ti.com/energy dsp dsp.ti.com industrial www.ti.com/industrial clocks and timers www.ti.com/clocks medical www.ti.com/medical interface interface.ti.com security www.ti.com/security logic logic.ti.com space, avionics and defense www.ti.com/space-avionics-defense power mgmt power.ti.com transportation and www.ti.com/automotive automotive microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com wireless www.ti.com/wireless-apps rf/if and zigbee ? solutions www.ti.com/lprf ti e2e community home page e2e.ti.com mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2011, texas instruments incorporated |
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